公开(公告)号：US20230154839A1

公开(公告)日：2023-05-18

申请号：US17529972

申请日：2021-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TSUCHIYA ,  Shuuichi KARIYAZAKI

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L24/13

Abstract: A semiconductor device includes a wiring substrate having: a first wiring layer having pads; and a second wiring layer having wirings and via-lands. The via-lands include: first-row via-lands connected to first-row pads of the pads, respectively; and second-row via-lands connected to the second-row pads of the pads, respectively. In the perspective plan view, the first-row via-lands have: first via-lands arranged such that a center of each of the first via-lands is shifted in a direction away from a first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad; and second via-lands arranged such that a center of each of the second via-lands arranged at a position closer to the first side than the first via-land. In the perspective plan view, the first and second via-lands are alternately arranged in a first direction along the first side.

公开(公告)号：US20190115295A1

公开(公告)日：2019-04-18

申请号：US16057724

申请日：2018-08-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI ,  Keita TSUCHIYA ,  Yoshitaka OKAYASU ,  Wataru SHIROI

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled.

公开(公告)号：US20140159224A1

公开(公告)日：2014-06-12

申请号：US14093337

申请日：2013-11-29

Applicant: Renesas Electronics Corporation

Inventor： Makoto OKADA ,  Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Masafumi SUZUHARA ,  Naoko SERA

IPC: H01L23/02 ,  H01L23/498 ,  H01L23/28

CPC classification number: H01L25/0655 ,  H01L23/02 ,  H01L23/04 ,  H01L23/055 ,  H01L23/28 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/33 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2924/1015 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/167 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device in which warpage is less likely to occur. In the semiconductor device, two semiconductor chips are mounted over a diagonal of a substrate and one of the semiconductor chips lies over the intersection of the two diagonals of the substrate. The semiconductor device gives a solution to the following problem. In order to implement a semiconductor device with a plurality of semiconductor chips mounted on a substrate, generally the substrate must have a larger area. If the area of the substrate is increased without an increase in its thickness, warpage or deformation of the semiconductor device is more likely to occur. It is difficult or impossible to mount a warped or deformed semiconductor device over a wiring substrate.

Abstract translation: 其中翘曲不太可能发生的半导体器件。 在半导体器件中，两个半导体芯片安装在衬底的对角线上，并且半导体芯片之一位于衬底的两个对角线的交叉点之上。 半导体器件给出了以下问题的解决方案。 为了实现具有安装在基板上的多个半导体芯片的半导体器件，通常基板必须具有更大的面积。 如果基板的面积增加而不增加其厚度，则更可能发生半导体器件的翘曲或变形。 将翘曲或变形的半导体器件安装在布线基板上是困难或不可能的。

公开(公告)号：US20250046741A1

公开(公告)日：2025-02-06

申请号：US18775102

申请日：2024-07-17

Applicant: Renesas Electronics Corporation

Inventor： Keita TSUCHIYA ,  Shuuichi KARIYAZAKI ,  Kazuo SAKAMOTO

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/528

Abstract: The performance of a semiconductor device can be improved. A plurality of protruding electrodes of a semiconductor chip includes: a plurality of first protruding electrodes arranged at positions overlapping a first region of an insulating layer, a plurality of second protruding electrodes arranged at positions overlapping a second region of the insulating layer, and a plurality of third protruding electrodes arranged at positions overlapping a third region of the insulating layer. The plurality of first protruding electrodes is arranged at a first pitch, the plurality of second protruding electrodes is arranged at a second pitch, and the plurality of third protruding electrodes is arranged at a third pitch different from each of the first pitch and the second pitch.

公开(公告)号：US20220375804A1

公开(公告)日：2022-11-24

申请号：US17326829

申请日：2021-05-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoichi ISOZUMI ,  Takafumi BETSUI ,  Shuuichi KARIYAZAKI

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/64 ,  H01L23/538

Abstract: A semiconductor apparatus includes a mounting board, a system on chip (SOC) package and a memory package which are provided on the mounting board. The SOC package includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The semiconductor apparatus further includes a signal wiring line through which a signal between the semiconductor chip and the memory package is transmitted, being provided on the package substrate and in the mounting board and a measurement terminal connected to the signal wiring line on main surface of the package substrate.

公开(公告)号：US20220223508A1

公开(公告)日：2022-07-14

申请号：US17144897

申请日：2021-01-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Wataru SHIROI ,  Shuuichi KARIYAZAKI

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

公开(公告)号：US20160218083A1

公开(公告)日：2016-07-28

申请号：US14967463

申请日：2015-12-14

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Ryuichi OIKAWA ,  Kenichi KUBOYAMA

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3025 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.

Abstract translation: 为了提高耦合在半导体芯片之间的插入器的信号传输的可靠性。 在设置在插入件的第一布线层中的信号线的两个相邻侧上设置参考电位布线和参考电位布线。 此外，在设置在插入器的第二布线层中的信号线的两个相邻侧上设置参考电位布线和参考电位布线。 此外，信号布线和信号布线在平面图中彼此交叉。 第一布线层的参考电位布线和第二布线层的参考电位布线在其交叉部分的周围彼此耦合。

公开(公告)号：US20150076684A1

公开(公告)日：2015-03-19

申请号：US14553835

申请日：2014-11-25

Applicant: Renesas Electronics Corporation

Inventor： Makoto Okada ,  Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Masafumi SUZUHARA ,  Naoko SERA

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/04

CPC classification number: H01L25/0655 ,  H01L23/02 ,  H01L23/04 ,  H01L23/055 ,  H01L23/28 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/33 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2924/1015 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/167 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, anda fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.

Abstract translation: 半导体器件包括主表面，与主表面相对的后表面，主表面上的第一侧，与第一侧相对的第二侧，第一侧和第二侧之间的第三侧，与第一侧相对的第四侧 在第三侧，在第一侧面和第三面之间的主表面的周边上的第一点，在第二侧面和第四侧面之间的主表面的周边上的第二点， 第一侧面和第四侧面之间的主表面以及位于第三侧面和第二侧面之间的主表面周边的第四点，设置在基板的主表面上的第一半导体芯片和第二半导体芯片 设置在基板的主表面上。

公开(公告)号：US20230187330A1

公开(公告)日：2023-06-15

申请号：US18163617

申请日：2023-02-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Wataru SHIROI ,  Shuuichi KARIYAZAKI

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/15 ,  H01L23/49816 ,  H01L23/49894

Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

公开(公告)号：US20220139877A1

公开(公告)日：2022-05-05

申请号：US17507271

申请日：2021-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.