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公开(公告)号：US20160249005A1
公开(公告)日：2016-08-25
申请号：US14961603
申请日：2015-12-07
Applicant: Renesas Electronics Corporation
Inventor： Osamu MATSUMOTO , Fukashi MORISHITA
IPC: H04N5/3745 , H04N5/63 , H04N5/378
CPC classification number: H04N5/378 , H04N5/3658
Abstract: In a CMOS image sensor, a plurality of bias circuits are dispersedly arranged in an arrangement region of column circuits corresponding to each column of a pixel array. Each bias circuit generates a bias voltage on the basis of a reference current which has been input and supplies the generated bias voltage to the corresponding column circuit 10 which is arranged in the vicinity. Thereby, luminance unevenness of a picked-up image caused by an IR drop of a ground wire for the column circuits is reduced.
Abstract translation: 在CMOS图像传感器中，多个偏置电路分散布置在与像素阵列的每列对应的列电路的布置区域中。 每个偏置电路基于已经输入的参考电流产生偏置电压，并将产生的偏置电压提供给布置在附近的对应的列电路10。 由此，降低了由列电路的接地线的IR下降引起的拍摄图像的亮度不均匀性。
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公开(公告)号：US20180152656A1
公开(公告)日：2018-05-31
申请号：US15797085
申请日：2017-10-30
Applicant: Renesas Electronics Corporation
Inventor： Osamu MATSUMOTO , Fukashi MORISHITA
CPC classification number: H04N5/378 , H03M1/123 , H03M1/46 , H03M1/466 , H03M1/682 , H03M1/765 , H04N5/37455
Abstract: Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor. The switch array is coupled to a second electrode of each of the first and second capacitors and is adapted to generate the analog reference signal at the output node by selectively applying a first reference voltage. The third capacitor is coupled to the second electrode of the split capacitor. The multiplexer is coupled to a second electrode of the third capacitor and is adapted to generate the analog reference signal at the output node by selectively applying a second reference voltage.
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公开(公告)号：US20130265180A1
公开(公告)日：2013-10-10
申请号：US13794308
申请日：2013-03-11
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Takashi MATSUMOTO , Masao ITO , Osamu MATSUMOTO , Hiroto SUZUKI
CPC classification number: H03M1/38 , H03M1/0697 , H03M1/46
Abstract: A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period.
Abstract translation: 在逐次逼近寄存器A / D转换器的操作基于集成电路中的电路定时受到影响的定时，获得N位输出的逐次逼近寄存器A / D转换器中断操作。 A / D转换器将采样信号和比较参考电压进行比较，其中采样模拟信号的采样周期，将采样信号顺序地与每个位的比较电压相比较的N个状态的比较周期 ，以及比较期间M州的储备期。 当操作暂时中断时，A / D转换器执行位的比较操作，而在保留期间不进行比较。
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公开(公告)号：US20200244908A1
公开(公告)日：2020-07-30
申请号：US16737527
申请日：2020-01-08
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Osamu MATSUMOTO , Masanori OTSUKA , Fukashi MORISHITA
Abstract: A solid-state imaging device capable of suppressing variations in reference voltages and improving performance of reference voltages is provided. According to one embodiment, the solid-state imaging device includes a pixel outputting a luminance signal voltage corresponding to an amount of incident light, reference voltages, a reference voltage generation circuit outputting a ramp signal and an inverse ramp signal, and an AD converter, and the AD converter includes a comparator including an amplifier coupled to one input terminal, a reference voltage and an input terminal coupled to each of the ramp signals via a capacitor, and an input terminal coupled to each of the reference voltage and the ramp signal via a capacitor, and a ramp current cancel circuit coupled to each of the reference voltages via a cancel capacitor.
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