公开(公告)号：US20120196424A1

公开(公告)日：2012-08-02

申请号：US13017108

申请日：2011-01-31

申请人： Rishikesh Krishnan ,  Joseph F. Shepard, JR. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

发明人： Rishikesh Krishnan ,  Joseph F. Shepard, JR. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

IPC分类号： H01L21/02

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

摘要翻译： 一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

公开(公告)号：US08241981B1

公开(公告)日：2012-08-14

申请号：US13017108

申请日：2011-01-31

申请人： Rishikesh Krishnan ,  Joseph F. Shepard, Jr. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

发明人： Rishikesh Krishnan ,  Joseph F. Shepard, Jr. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

摘要翻译： 一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

公开(公告)号：US08981565B2

公开(公告)日：2015-03-17

申请号：US13428184

申请日：2012-03-23

申请人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet Serkan Ozcan ,  Zhen Zhang

发明人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet Serkan Ozcan ,  Zhen Zhang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L29/665 ,  H01L21/02381 ,  H01L21/02631 ,  H01L21/244 ,  H01L21/28518 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/161

摘要： In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

摘要翻译： 一方面，制造金属硅化物的方法包括以下步骤。 提供从由硅和硅锗组成的组中选择的半导体材料。 一种或多种金属沉积在半导体材料上。 在足以使金属与半导体材料反应的温度和持续时间进行第一退火以形成包括由金属和半导体材料形成的合金的非晶层，其中， 进行第一退火低于形成合金的结晶相的温度。 使用蚀刻来选择性地去除金属的未反应部分。 在足以使合金结晶形成金属硅化物的温度和持续时间内进行第二次退火。 还提供了器件触点和制造FET器件的方法。

公开(公告)号：US20130249099A1

公开(公告)日：2013-09-26

申请号：US13428184

申请日：2012-03-23

申请人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet Serkan Ozcan ,  Zhen Zhang

发明人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet Serkan Ozcan ,  Zhen Zhang

IPC分类号： H01L23/48 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/665 ,  H01L21/02381 ,  H01L21/02631 ,  H01L21/244 ,  H01L21/28518 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/161

摘要： In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

公开(公告)号：US08415250B2

公开(公告)日：2013-04-09

申请号：US13097459

申请日：2011-04-29

申请人： Emre Alptekin ,  Dong-Ick Lee ,  Viraj Yashawant Sardesai ,  Cung Do Tran ,  Jian Yu ,  Reinaldo Ariel Vega ,  Rajasekhar Venigalla

发明人： Emre Alptekin ,  Dong-Ick Lee ,  Viraj Yashawant Sardesai ,  Cung Do Tran ,  Jian Yu ,  Reinaldo Ariel Vega ,  Rajasekhar Venigalla

IPC分类号： H01L29/417

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

摘要翻译： 提供了一种用于制造用于半导体器件的硅化物触点的结构和方法。 具体地，该结构和方法涉及利用化学气相沉积（CVD）和退火以在半导体场效应晶体管（FET）（例如源极和漏极区域）的区域上选择性地形成不同形状的硅化物接触。 硅化物触点的形状是可以被操纵以降低接触电阻的关键因素。 因此，该结构和方法提供具有低接触电阻的不同形状的硅化物触点，其中硅化物触点还减轻漏电流以增强低功率应用中的FET的效用和性能。

公开(公告)号：US20120273798A1

公开(公告)日：2012-11-01

申请号：US13097459

申请日：2011-04-29

申请人： Emre Alptekin ,  Dong-Ick Lee ,  Viraj Yashawant Sardesai ,  Cung Do Tran ,  Jian Yu ,  Reinaldo Ariel Vega ,  Rajasekhar Venigalla

发明人： Emre Alptekin ,  Dong-Ick Lee ,  Viraj Yashawant Sardesai ,  Cung Do Tran ,  Jian Yu ,  Reinaldo Ariel Vega ,  Rajasekhar Venigalla

IPC分类号： H01L29/772

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

摘要翻译： 提供了一种用于制造用于半导体器件的硅化物触点的结构和方法。 具体地，该结构和方法涉及利用化学气相沉积（CVD）和退火以在半导体场效应晶体管（FET）（例如源极和漏极区域）的区域上选择性地形成不同形状的硅化物接触。 硅化物触点的形状是可以被操纵以降低接触电阻的关键因素。 因此，该结构和方法提供具有低接触电阻的不同形状的硅化物触点，其中硅化物触点还减轻漏电流以增强低功率应用中的FET的效用和性能。