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    METHOD OF FABRICATING A DEEP TRENCH (DT) METAL-INSULATOR-METAL (MIM) CAPACITOR
    1.
    发明申请
    METHOD OF FABRICATING A DEEP TRENCH (DT) METAL-INSULATOR-METAL (MIM) CAPACITOR 失效
    深层金属（金属）绝缘子（MIM）电容器的制造方法

    公开(公告)号：US20120196424A1

    公开(公告)日：2012-08-02

    申请号：US13017108

    申请日：2011-01-31

    申请人： Rishikesh Krishnan ,  Joseph F. Shepard, JR. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

    发明人： Rishikesh Krishnan ,  Joseph F. Shepard, JR. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

    IPC分类号： H01L21/02

    CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

    摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

    摘要翻译： 一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

    Method of fabricating a deep trench (DT) metal-insulator-metal (MIM) capacitor
    2.
    发明授权
    Method of fabricating a deep trench (DT) metal-insulator-metal (MIM) capacitor 失效
    制造深沟槽（DT）金属 - 绝缘体 - 金属（MIM）电容器的方法

    公开(公告)号：US08241981B1

    公开(公告)日：2012-08-14

    申请号：US13017108

    申请日：2011-01-31

    申请人： Rishikesh Krishnan ,  Joseph F. Shepard, Jr. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

    发明人： Rishikesh Krishnan ,  Joseph F. Shepard, Jr. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

    摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

    摘要翻译： 一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

    Insulating layers on different semiconductor materials
    3.
    发明授权
    Insulating layers on different semiconductor materials 失效
    绝缘层在不同的半导体材料上

    公开(公告)号：US08592325B2

    公开(公告)日：2013-11-26

    申请号：US12685332

    申请日：2010-01-11

    申请人： Joseph F. Shepard, Jr. ,  Siddarth A. Krishnan ,  Rishikesh Krishnan ,  Michael P. Chudzik

    发明人： Joseph F. Shepard, Jr. ,  Siddarth A. Krishnan ,  Rishikesh Krishnan ,  Michael P. Chudzik

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02164 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/28255 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/66651

    摘要： A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.

    摘要翻译： 在不同半导体材料上制造绝缘层的方法包括提供其上设置有第一材料和第二材料的基底，所述第二材料具有与第一材料不同的化学组成; 将大约恒定厚度的连续牺牲层非外延沉积到第一材料和第二材料上，然后将牺牲层转变成基本上由SiO 2组成的层，而不将氧化物超过10埃，进入第二材料。 一种结构包括：保形地设置在硅层和硅锗层上的氮化硅膜; SiO 2层设置在氮化硅膜上。

    INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS
    4.
    发明申请
    INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS 失效
    在不同的半导体材料上绝缘层

    公开(公告)号：US20110169141A1

    公开(公告)日：2011-07-14

    申请号：US12685332

    申请日：2010-01-11

    申请人： Joseph F. Shepard, JR. ,  Siddarth A. Krishnan ,  Rishikesh Krishnan ,  Michael P. Chudzik

    发明人： Joseph F. Shepard, JR. ,  Siddarth A. Krishnan ,  Rishikesh Krishnan ,  Michael P. Chudzik

    IPC分类号： H01L23/00 ,  H01L21/316

    CPC分类号： H01L21/02164 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/28255 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/66651

    摘要： A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.

    摘要翻译： 在不同半导体材料上制造绝缘层的方法包括提供其上设置有第一材料和第二材料的基底，所述第二材料具有与第一材料不同的化学组成; 将大约恒定厚度的连续牺牲层非外延沉积到第一材料和第二材料上，然后将牺牲层转变成基本上由SiO 2组成的层，而不将氧化物超过10埃，进入第二材料。 一种结构包括：保形地设置在硅层和硅锗层上的氮化硅膜; SiO 2层设置在氮化硅膜上。

    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
    6.
    发明申请
    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT 有权
    具有降低闸门泄漏电流的更换门

    公开(公告)号：US20120181630A1

    公开(公告)日：2012-07-19

    申请号：US13006656

    申请日：2011-01-14

    申请人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

    发明人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

    摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

    摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

    NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE
    10.
    发明申请
    NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE 有权
    使用高K门电介质和金属门的非易失性存储器结构

    公开(公告)号：US20130105879A1

    公开(公告)日：2013-05-02

    申请号：US13326767

    申请日：2011-12-15

    申请人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

    发明人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

    IPC分类号： H01L29/788 ,  H01L21/28

    CPC分类号： H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

    摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

    摘要翻译： 用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和用于非易失性随机存取存储器（NVRAM）器件的高k隧道电介质）同时形成在半导体衬底上。 随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。 沉积并图案化平坦化介电层，并且去除一次性材料部分。 控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。 导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。 或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。