公开(公告)号：US20120196424A1

公开(公告)日：2012-08-02

申请号：US13017108

申请日：2011-01-31

申请人： Rishikesh Krishnan ,  Joseph F. Shepard, JR. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

发明人： Rishikesh Krishnan ,  Joseph F. Shepard, JR. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

IPC分类号： H01L21/02

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

摘要翻译： 一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

公开(公告)号：US08241981B1

公开(公告)日：2012-08-14

申请号：US13017108

申请日：2011-01-31

申请人： Rishikesh Krishnan ,  Joseph F. Shepard, Jr. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

发明人： Rishikesh Krishnan ,  Joseph F. Shepard, Jr. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

摘要翻译： 一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

公开(公告)号：US08377790B2

公开(公告)日：2013-02-19

申请号：US13014995

申请日：2011-01-27

申请人： Narasimhulu Kanike ,  Mark R. Visokay ,  Oh-Jung Kwon

发明人： Narasimhulu Kanike ,  Mark R. Visokay ,  Oh-Jung Kwon

IPC分类号： H01L21/20

CPC分类号： H01L28/20 ,  H01L21/76224 ,  H01L23/5256 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing.

摘要翻译： 一种方法包括提供其上具有绝缘层的基板; 在所述衬底的第一区域中形成第一沟槽和在所述衬底的第二区域中形成第二沟槽; 沿着沟槽的侧面的氧化物的热生长层; 用多晶硅材料填充第一沟槽和第二沟槽，平坦化多晶硅材料，以及在第一区域和第二区域之间产生浅沟槽隔离，其中仅在步骤之后才执行产生浅沟槽隔离的步骤f） 的d）填充和e）平面化。

公开(公告)号：US07564086B2

公开(公告)日：2009-07-21

申请号：US11566360

申请日：2006-12-04

申请人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Ali Babar Khan ,  Deok-kee Kim

发明人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Ali Babar Khan ,  Deok-kee Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/10867 ,  H01L27/10888

摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

摘要翻译： 衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO） 沟槽的顶部并且在字线的方向上延伸超过沟槽。 以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。

公开(公告)号：US20080157216A1

公开(公告)日：2008-07-03

申请号：US11619357

申请日：2007-01-03

申请人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

发明人： Deok-kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

IPC分类号： H01L27/092 ,  H01L21/762

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

公开(公告)号：US20080070360A1

公开(公告)日：2008-03-20

申请号：US11533018

申请日：2006-09-19

申请人： Oh-Jung Kwon ,  O Sung Kwon

发明人： Oh-Jung Kwon ,  O Sung Kwon

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming silicide contacts for a complementary metal oxide semiconductor (CMOS) device includes selectively forming a protective layer over faceted surfaces of an embedded SiGe (eSiGe) region of a substrate, the eSiGe region comprising a compressive stress inducing layer in a PFET portion of the CMOS device, wherein the faceted surfaces are disposed adjacent shallow trench isolation (STI) regions used to separate NFET regions from PFET regions of the CMOS device; depositing a metal layer for silicide formation over the CMOS device; and annealing the CMOS device to form silicide, wherein the protective layer formed over the faceted surfaces prevents the formation of silicide thereon.

摘要翻译： 形成用于互补金属氧化物半导体（CMOS）器件的硅化物触点的方法包括在衬底的嵌入式SiGe（eSiGe）区域的刻面上选择性地形成保护层，eSiGe区域包括PFET部分中的压应力诱导层 其中所述刻面被设置在用于将NFET区与CMOS器件的PFET区分离的浅沟槽隔离（STI）区域附近; 在CMOS器件上沉积用于硅化物形成的金属层; 并且对CMOS器件进行退火以形成硅化物，其中形成在刻面上的保护层防止其上形成硅化物。

公开(公告)号：US20070235792A1

公开(公告)日：2007-10-11

申请号：US11566360

申请日：2006-12-04

申请人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Ho ,  Babar Khan ,  Deok-kee Kim

发明人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Ho ,  Babar Khan ,  Deok-kee Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/10867 ,  H01L27/10888

摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

摘要翻译： 衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO） 沟槽的顶部并且在字线的方向上延伸超过沟槽。 以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。

公开(公告)号：US07153737B2

公开(公告)日：2006-12-26

申请号：US10905684

申请日：2005-01-17

申请人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Babar Ali Khan ,  Deok-kee Kim

发明人： Oh-Jung Kwon ,  Kim Bosang ,  Herbert Lei Ho ,  Babar Ali Khan ,  Deok-kee Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/10888

摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

摘要翻译： 衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO） 沟槽的顶部并且在字线的方向上延伸超过沟槽。 以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。

公开(公告)号：US20050202672A1

公开(公告)日：2005-09-15

申请号：US10708530

申请日：2004-03-10

申请人： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

发明人： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L27/10894 ,  H01L27/10861 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprised of at least one semiconductor memory array and logic circuits. The memory array includes electrically conductive word lines. The logic circuits include logic transistors with electrically conductive gates. The gates of the logic transistors and the word lines are composed of polysilicon and a metal layer. The metal layer is thicker than the polysilicon layer in the word lines; and the metal layer is thinner than the polysilicon layer in the gates of the logic transistors.

摘要翻译： 一种由至少一个半导体存储器阵列和逻辑电路组成的集成电路。 存储器阵列包括导电字线。 逻辑电路包括具有导电栅极的逻辑晶体管。 逻辑晶体管和字线的栅极由多晶硅和金属层组成。 金属层比字线中的多晶硅层厚; 并且金属层比逻辑晶体管的栅极中的多晶硅层薄。

公开(公告)号：US10115725B2

公开(公告)日：2018-10-30

申请号：US13470380

申请日：2012-05-14

申请人： Oh-Jung Kwon

发明人： Oh-Jung Kwon

IPC分类号： H01L27/108 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

摘要： A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled.