公开(公告)号：US20070046369A1

公开(公告)日：2007-03-01

申请号：US11459339

申请日：2006-07-22

申请人： Robert Schober ,  Ion Opris ,  Francois Krummenacher

发明人： Robert Schober ,  Ion Opris ,  Francois Krummenacher

IPC分类号： H03F21/00

CPC分类号： H03F3/195 ,  G06K19/0707 ,  G06K19/0713 ,  G06K19/0723 ,  H03F1/0205 ,  H03F1/223 ,  H03F3/70 ,  H03F21/00 ,  H03F2200/162 ,  H03F2200/513

摘要： A method and apparatus for an ultra-high sensitivity, low cost, passive (no battery) low-power energy harvesting data transmitting circuit energy, such as a RFID (Radio Frequency IDentification) tag integrated circuit “chip.” By using combinations of special purpose design enhancements, the low-power energy harvesting passive data transmitting circuit, such as the RFID tag chip, operates in the sub-microwatt power range. The chip power should be derived from a low-microwatt per square centimeter RF field radiated to the RFID tag antenna from the tag reader (interrogator) or derived from a suitable low signal source, such as a sonic transducer (e.g., a piezoelectric transducer or a low level DC source, such as a bimetallic or chemical source).

摘要翻译： 一种用于超高灵敏度，低成本，无源（无电池）低功率能量采集数据传输电路能量的方法和装置，例如RFID（射频识别）标签集成电路“芯片”。 通过使用特殊设计增强功能的组合，低功率能量采集无源数据传输电路（如RFID标签芯片）在亚微瓦功率范围内工作。 芯片功率应来自于从标签读取器（询问器）辐射到RFID标签天线的低平方厘米RF场的低微瓦，或者衍生自合适的低信号源，例如声音换能器（例如，压电换能器或 低级DC源，例如双金属或化学源）。

公开(公告)号：US20120212064A1

公开(公告)日：2012-08-23

申请号：US13277977

申请日：2011-10-20

申请人： Sorin Andrei Spanoche ,  Kent Kernahan ,  Ion Opris ,  Paul Scrobohaci ,  Peter Curzon ,  Richard Moeller ,  Shiloh Hawley ,  Aldrin Aviananda ,  David Stewart ,  Felipe Fuks ,  Marc Elpel

发明人： Sorin Andrei Spanoche ,  Kent Kernahan ,  Ion Opris ,  Paul Scrobohaci ,  Peter Curzon ,  Richard Moeller ,  Shiloh Hawley ,  Aldrin Aviananda ,  David Stewart ,  Felipe Fuks ,  Marc Elpel

IPC分类号： H02J1/00 ,  H02M7/537

CPC分类号： H02M7/48 ,  H02J3/382 ,  H02J3/383 ,  Y02E10/563 ,  Y10T307/707

摘要： Methods, apparatus and systems for controlling a photovoltaic panel, to output three-phase power while ensuring the power source operates safely include determining a temperature of the photovoltaic panel, determining a voltage provided from the photovoltaic panel, determining a parameter based on the voltage and the temperature and controlling a DC to three-phase power converter based on the determined parameter. The three-phase power converter may be a pulse amplitude modulated current converter (PAMCC), configured to output first, second and third pulse amplitude modulated current pulse from three terminals controlled in timing and phase so that when respective outputs of multiple PAMCCs are connected, each phase of the plurality of PAMCCs is demodulated to produce a three-phase alternating current output. The PAMCC may be controlled through tables of pulse durations based on the determined parameter. The voltage output may be controlled through a fast control loop and through a slower control loop.

摘要翻译： 用于控制光伏面板，用于输出三相电力同时确保电源运行安全的方法，装置和系统包括确定光伏面板的温度，确定从光伏面板提供的电压，基于电压确定参数，以及 根据确定的参数控制直流到三相电力转换器的温度。 三相功率转换器可以是脉冲幅度调制电流转换器（PAMCC），被配置为从定时和相位控制的三个端子输出第一，第二和第三脉冲幅度调制电流脉冲，使得当连接多个PAMCC的相应输出时， 多个PAMCC的每个相位被解调以产生三相交流输出。 基于确定的参数可以通过脉冲持续时间表来控制PAMCC。 电压输出可以通过快速控制回路和较慢的控制回路进行控制。

公开(公告)号：US06933778B2

公开(公告)日：2005-08-23

申请号：US10921016

申请日：2004-08-18

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03F3/217 ,  H03M3/02 ,  H03M7/32 ,  H03F3/38

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.In another aspect of the invention; additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

公开(公告)号：US20060158365A1

公开(公告)日：2006-07-20

申请号：US11316636

申请日：2005-12-21

申请人： Kent Kernahan ,  Xuecheng Jin ,  Ping Lo ,  Ion Opris ,  Sorin Spanoche

发明人： Kent Kernahan ,  Xuecheng Jin ,  Ping Lo ,  Ion Opris ,  Sorin Spanoche

IPC分类号： H03M1/12

CPC分类号： H03M1/38

摘要： Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal and to thereby provide fairly good guesses.

摘要翻译： 公开了用于在较短时间内和/或具有比使用基于二进制搜索的常规顺序近似方法的可比较模数转换的功耗更少的时间和/或执行模数转换的方法和装置。 在一个实施例中，预测猜测被提供为数字第一信号。 数字第一信号被转换（D / A）到对应的模拟猜测信号。 比较模拟猜测信号和接收的模拟输入采样信号。 比较结果用于在下一个周期中提高初始提供的猜测。 如果初始猜测在模拟输入采样信号的实际幅度的一定范围内，则消耗更少的周期和更少的功率。 在一个实施例中，数字建模器用于对模拟输入采样信号的过程进行建模，从而提供相当好的猜测。

公开(公告)号：US06933870B2

公开(公告)日：2005-08-23

申请号：US09768674

申请日：2001-01-24

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03F3/217 ,  H03M3/02 ,  H03M7/32 ,  H03M3/00

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

摘要翻译： 描述了一种创建高效数字放大​​器的系统和方法，该数字放大器可以采用模拟或数字输入，并且产生用于驱动扬声器或其他低阻抗负载的输入的高功率精确表示。 一旦检测到输出转换，该系统采用转换检测器和延迟单元，其允许信号调制器的比较器忽略其输入以用于预定数量的后续时钟周期。 通过使用更快的时钟和可变时钟周期跳过比较器的输出转换，实现了用于噪声整形的反馈时钟周期的更好的分辨率。 时钟周期的更好的分辨率允许本发明采用比先前可能的更积极的噪声整形。 在本发明的另一方面，通过使用功率输出级的共同桥接实现，通过改进配置桥以创建3态条件而不是传统的2状态来获得附加的Δ-Σ调制器噪声抑制。 通过彼此独立地控制桥的两半，具有3个状态的输出改善了噪声整形性能。

公开(公告)号：US06864815B2

公开(公告)日：2005-03-08

申请号：US10886325

申请日：2004-07-07

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03F3/217 ,  H03M3/02 ,  H03M7/32 ,  H03M1/00 ,  H03M3/00

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

摘要翻译： 描述了一种创建高效数字放大​​器的系统和方法，该数字放大器可以采用模拟或数字输入，并且产生用于驱动扬声器或其他低阻抗负载的输入的高功率精确表示。 一旦检测到输出转换，该系统采用转换检测器和延迟单元，其允许信号调制器的比较器忽略其输入以用于预定数量的后续时钟周期。 通过使用更快的时钟和可变时钟周期跳过比较器的输出转换，实现了用于噪声整形的反馈时钟周期的更好的分辨率。 时钟周期的更好的分辨率允许本发明采用比先前可能的更积极的噪声整形。在本发明的另一方面，通过使用功率输出级的公共桥接实现来获得附加的Δ-Σ调制器噪声抑制， 改进配置桥以创建3状态而不是传统的2状态。 通过彼此独立地控制桥的两半，具有3个状态的输出改善了噪声整形性能。

公开(公告)号：US06496127B2

公开(公告)日：2002-12-17

申请号：US09768674

申请日：2001-01-24

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03M106

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible. In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

摘要翻译： 描述了一种创建高效数字放大​​器的系统和方法，该数字放大器可以采用模拟或数字输入，并且产生用于驱动扬声器或其他低阻抗负载的输入的高功率精确表示。 一旦检测到输出转换，该系统采用转换检测器和延迟单元，其允许信号调制器的比较器忽略其输入以用于预定数量的后续时钟周期。 通过使用更快的时钟和可变时钟周期跳过比较器的输出转换，实现了用于噪声整形的反馈时钟周期的更好的分辨率。 时钟周期的更好的分辨率允许本发明采用比先前可能的更积极的噪声整形。在本发明的另一方面，通过使用功率输出级的公共桥接实现来获得附加的Δ-Σ调制器噪声抑制， 改进配置桥以创建3状态而不是传统的2状态。 通过彼此独立地控制桥的两半，具有3个状态的输出改善了噪声整形性能。

公开(公告)号：US06791404B1

公开(公告)日：2004-09-14

申请号：US09346361

申请日：1999-07-01

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03F338

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible. In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

公开(公告)号：US20120293017A1

公开(公告)日：2012-11-22

申请号：US13453739

申请日：2012-04-23

申请人： David Lidsky ,  Ognjen Djekic ,  Ion Opris ,  Budong You ,  Anthony J. Stratakos ,  Alexander Ikriannikov ,  Biljana Beronja ,  Trey Roessig

发明人： David Lidsky ,  Ognjen Djekic ,  Ion Opris ,  Budong You ,  Anthony J. Stratakos ,  Alexander Ikriannikov ,  Biljana Beronja ,  Trey Roessig

IPC分类号： H01H35/00

CPC分类号： H01L27/0266 ,  G01R19/16552 ,  H02H3/087 ,  H02H3/18 ,  H02H3/202 ,  H02H3/42 ,  Y10T307/826 ,  Y10T307/832 ,  Y10T307/858 ,  Y10T307/865

摘要： Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.

摘要翻译： 公开了可以在组件之间耦合切换机构的系统，设备，电路，部件，机构和过程。 开关机构被配置为具有导通状态或截止状态，其中导通状态允许电流沿着电流路径通过。 监测机构具有耦合以感测当前路径上的电特性的一个或多个感测输入。 作为示例，电特性可以是电流，电压和/或功率。 监视机构被配置为输出指示感测到的电特性的报告信号。 监控机制可以与芯片上的切换机制集成。

公开(公告)号：US20060238262A1

公开(公告)日：2006-10-26

申请号：US11115023

申请日：2005-04-25

申请人： Ion Opris

发明人： Ion Opris

IPC分类号： H03L7/00

CPC分类号： H03L7/23 ,  H03L7/0995 ,  H03L7/18

摘要： Phase-locked loop (PLL) methods and apparatus are described for generating multiple output clocks synchronized to different frequencies of multiple input signals, wherein the multiple-output PLL employs a single voltage controlled oscillator (VCO). In an embodiment, the base module generates signals with a controlled frequency, multiple equidistant phase, and reduced duty cycles. Frequency dividers using barrel-shifters driven by an early-late detector combined with a left/right “one hot” shift-register or driven by an early-late detector combined with up-down counter/decoder are also disclosed.

摘要翻译： 描述了锁相环（PLL）方法和装置，用于产生与多个输入信号的不同频率同步的多个输出时钟，其中多输出PLL采用单个压控振荡器（VCO）。 在一个实施例中，基本模块产生具有受控频率，多等距相位和减小占空比的信号。 还公开了使用由早期检测器驱动的桶形移位器的分频器，其与左/右“一个热”移位寄存器组合或由与升降计数器/解码器组合的早期检测器驱动。