公开(公告)号：US06807119B2

公开(公告)日：2004-10-19

申请号：US10325737

申请日：2002-12-23

申请人： Luca Fasoli ,  Alper Ilkbahar ,  Roy Scheuerlein

发明人： Luca Fasoli ,  Alper Ilkbahar ,  Roy Scheuerlein

IPC分类号： G11C700

CPC分类号： G11C16/0416

摘要： An array of transistors includes a plurality of charge storage transistors and a plurality of dummy transistors interspersed with the plurality of charge storage transistors. Each of the plurality of the dummy transistors is made using the same photolithographic masking steps as each of the plurality of the charge storage transistors. A method of operating the array includes programming and/or erasing the array of transistors, and reading the plurality of charge storage transistors but not the plurality of dummy transistors.

公开(公告)号：US07132335B2

公开(公告)日：2006-11-07

申请号：US10965763

申请日：2004-10-18

申请人： Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker ,  Luca Fasoli

发明人： Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker ,  Luca Fasoli

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/792

摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

摘要翻译： 晶体管阵列包括多个晶体管，沿第一方向延伸的多个字线和沿第二方向延伸的多个位线。 每个晶体管包括源极，漏极，沟道和局部电荷存储电介质。 所述多个晶体管中的第一晶体管和所述多个晶体管中的第二晶体管共用公共源极/漏极。 第一晶体管的第一局部电荷存储电介质不与公共源极/漏极重叠，并且第二晶体管的第二局部电荷存储电介质与公共源极/漏极重叠。

公开(公告)号：US20070242511A1

公开(公告)日：2007-10-18

申请号：US11764793

申请日：2007-06-18

申请人： En-Hsing Chen ,  Andrew Walker ,  Roy Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli

发明人： En-Hsing Chen ,  Andrew Walker ,  Roy Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli

IPC分类号： G11C16/10

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US20060067127A1

公开(公告)日：2006-03-30

申请号：US10955049

申请日：2004-09-30

申请人： Luca Fasoli ,  Roy Scheuerlein ,  Alper Ilkbahar ,  En-Hsing Chen ,  Tanmay Kumar

发明人： Luca Fasoli ,  Roy Scheuerlein ,  Alper Ilkbahar ,  En-Hsing Chen ,  Tanmay Kumar

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C16/16

摘要： A method of programming a monolithic three-dimensional (3-D) memory having a plurality of levels of memory cells above a silicon substrate is disclosed. The method includes initializing a program voltage and program time interval; selecting a memory cell to be programmed within the three-dimensional memory having the plurality of levels of memory cells; applying a pulse having the program voltage and the program time interval to the selected memory cell; performing a read after write operation with respect to the selected memory cell to determine a measured threshold voltage value; and comparing the measured threshold voltage value to a minimum program voltage. In response to the comparison between the measured threshold voltage value and the minimum program voltage, the method further includes selectively applying at least one subsequent program pulse to the selected memory cell.

摘要翻译： 公开了一种在硅衬底上编程具有多层存储单元的单片三维（3-D）存储器的方法。 该方法包括初始化程序电压和程序时间间隔; 选择要在具有多个级别的存储器单元的三维存储器内编程的存储器单元; 将具有编程电压和程序时间间隔的脉冲施加到所选存储单元; 在对所选择的存储单元进行写操作之后执行读取以确定测量的阈值电压值; 以及将所测量的阈值电压值与最小编程电压进行比较。 响应于测量的阈值电压值和最小编程电压之间的比较，该方法还包括选择性地将至少一个后续编程脉冲施加到所选存储单元。

公开(公告)号：US06849905B2

公开(公告)日：2005-02-01

申请号：US10325951

申请日：2002-12-23

申请人： Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker ,  Luca Fasoli

发明人： Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker ,  Luca Fasoli

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/792 ,  H01L29/72

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/792

摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

摘要翻译： 晶体管阵列包括多个晶体管，沿第一方向延伸的多个字线和沿第二方向延伸的多个位线。 每个晶体管包括源极，漏极，沟道和局部电荷存储电介质。 所述多个晶体管中的第一晶体管和所述多个晶体管中的第二晶体管共用公共源极/漏极。 第一晶体管的第一局部电荷存储电介质不与公共源极/漏极重叠，并且第二晶体管的第二局部电荷存储电介质与公共源极/漏极重叠。

公开(公告)号：US20070263423A1

公开(公告)日：2007-11-15

申请号：US11764789

申请日：2007-06-18

申请人： Roy Scheuerlein ,  Alper Ilkbahar ,  Luca Fasoli

发明人： Roy Scheuerlein ,  Alper Ilkbahar ,  Luca Fasoli

IPC分类号： G11C5/06

CPC分类号： G11C7/18 ,  G11C16/0416 ,  G11C16/0466 ,  G11C17/12 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/77 ,  Y10S257/91

摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

摘要翻译： 三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。 分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。 全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。 位线段优选地共享到相关联的全局位线的垂直连接。 在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。 这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。

公开(公告)号：US20050128807A1

公开(公告)日：2005-06-16

申请号：US10729865

申请日：2003-12-05

申请人： En-Hsing Chen ,  Andrew Walker ,  Roy Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli ,  James Cleeves

发明人： En-Hsing Chen ,  Andrew Walker ,  Roy Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli ,  James Cleeves

IPC分类号： G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US20050122780A1

公开(公告)日：2005-06-09

申请号：US10729844

申请日：2003-12-05

申请人： En-Hsing Chen ,  Andrew Walker ,  Roy Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli

发明人： En-Hsing Chen ,  Andrew Walker ,  Roy Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli

IPC分类号： G11C5/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US20050079675A1

公开(公告)日：2005-04-14

申请号：US10965763

申请日：2004-10-18

申请人： Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew Walker ,  Luca Fasoli

发明人： Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew Walker ,  Luca Fasoli

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/792 ,  H01L21/00 ,  H01L21/31 ,  H01L21/469 ,  H01L21/84

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/792

摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

公开(公告)号：US20120106253A1

公开(公告)日：2012-05-03

申请号：US13348336

申请日：2012-01-11

申请人： Roy E. Scheuerlein ,  Alper Ilkbahar ,  Luca Fasoli

发明人： Roy E. Scheuerlein ,  Alper Ilkbahar ,  Luca Fasoli

IPC分类号： G11C5/06 ,  G11C16/04

CPC分类号： G11C7/18 ,  G11C16/0416 ,  G11C16/0466 ,  G11C17/12 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/77 ,  Y10S257/91

摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

摘要翻译： 三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。 分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。 全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。 位线段优选地共享到相关联的全局位线的垂直连接。 在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。 这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。