公开(公告)号：US12200922B2

公开(公告)日：2025-01-14

申请号：US18116883

申请日：2023-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

IPC: H10B12/00

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

公开(公告)号：US20250081429A1

公开(公告)日：2025-03-06

申请号：US18664753

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youmin Ban ,  Daeyoung Moon ,  Changwoo Seo ,  Suyoun Song ,  Hyungjun Hwang

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate, an active region defined by a device isolation layer within the substrate, a word line extending in a first horizontal direction within the substrate, a bit line extending on the substrate in a second horizontal direction intersecting with the first horizontal direction and including a metal-based conductive pattern, a first spacer on a sidewall of the metal-based conductive pattern, a second spacer on the first spacer, a direct contact in a direct contact hole exposing the active region and electrically connecting the bit line to the active region, and a buried spacer on a lower sidewall of the direct contact within the direct contact hole, wherein the second spacer contacts a sidewall of the direct contact on the sidewall of the direct contact.

公开(公告)号：US20220173107A1

公开(公告)日：2022-06-02

申请号：US17358055

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

IPC: H01L27/108

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

公开(公告)号：US11830567B2

公开(公告)日：2023-11-28

申请号：US17372697

申请日：2021-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwon Ma ,  Chunhyung Chung ,  Jamin Koo ,  Kyuwan Kim ,  Daeyoung Moon ,  Wonseok Yoo

IPC: G11C5/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

CPC classification number: G11C5/063 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/532 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482

Abstract: An integrated circuit device includes; word lines extending in a first direction across a substrate and spaced apart in a second direction different from the first direction, bit lines extending on the word lines in the second direction and spaced apart in the first direction, a first contact plug arranged among the bitlines, contacting a first active region of the substrate, having a first width, and having a first dopant concentration, and a second contact plug arranged among the bitlines, contacting a second active region of the substrate, having a second width, and having a second dopant concentration less than the first dopant concentration.

公开(公告)号：US11152058B2

公开(公告)日：2021-10-19

申请号：US16566002

申请日：2019-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US10453521B2

公开(公告)日：2019-10-22

申请号：US15417807

申请日：2017-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: H01L27/11 ,  G11C11/419 ,  H01L23/528 ,  H01L27/092 ,  G11C7/08

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20240389303A1

公开(公告)日：2024-11-21

申请号：US18663449

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Beomseo Kim

IPC: H10B12/00

Abstract: A semiconductor device includes an active region disposed in a substrate, a device isolation layer defining the active region, a gate structure disposed in the substrate and extending in a first horizontal direction to cross the active region, bit line structures crossing the gate structure and extending in a second horizontal direction, intersecting the first horizontal direction, and a contact plug between the bit line structures. The active region includes a first source/drain region, a second source/drain region, and a channel region. The first and second source/drain regions are spaced apart from each other by the gate structure. The first source/drain region includes a first lower region and a first upper region on the first lower region. The first lower region is a first crystal region, and the first upper region is a second crystal region, different from the first crystal region. The contact plug contacts the first upper region.

公开(公告)号：US11854610B2

公开(公告)日：2023-12-26

申请号：US18164199

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  H10B10/00 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092

CPC classification number: G11C11/419 ,  G11C7/08 ,  H01L23/5286 ,  H01L27/092 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20230247823A1

公开(公告)日：2023-08-03

申请号：US18056085

申请日：2022-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongkeun CHO ,  Jae Seong Park ,  Youngseok Kim ,  Young Sin Kim ,  Daeyoung Moon ,  Keum Joo Lee ,  Sung-Wook Jung ,  Sungduk Hong ,  Suhwan Hwang

IPC: H01L29/94 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063 ,  H01L27/10897

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area defined by a periphery of the cell area, the cell area including a dummy cell area and a normal cell area, and an active area defined by a cell element isolation film. The device includes a cell area separation film defining the cell area in the substrate, the dummy cell area defining a boundary with the cell area separation film between the normal cell area and the cell area separation film. The device includes a normal bit-line on the normal cell area and extending in a first direction, a dummy bit-line group on the dummy cell area, the dummy bit-line group including a plurality of dummy bit-lines extending in the first direction, and a plurality of storage contacts connected to the active area and located along a second direction perpendicular to the first direction.

公开(公告)号：US11581038B2

公开(公告)日：2023-02-14

申请号：US17412588

申请日：2021-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.