公开(公告)号：US11568903B2

公开(公告)日：2023-01-31

申请号：US17222024

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C16/34

Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

公开(公告)号：US11507448B2

公开(公告)日：2022-11-22

申请号：US16708988

申请日：2019-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejin Kim ,  Hyunjun Yoon

IPC: G06F11/07 ,  G06F12/0882 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4074 ,  G06F13/16

Abstract: A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.

公开(公告)号：US20230131700A1

公开(公告)日：2023-04-27

申请号：US18085963

申请日：2022-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C16/34

Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

公开(公告)号：US20220172775A1

公开(公告)日：2022-06-02

申请号：US17510828

申请日：2021-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoon PARK ,  Sungwon Yun ,  Hyunjun Yoon ,  Wontaeck Jung

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A method of operating a memory device that performs a plurality of program loops for a plurality of memory cells includes applying a first program pulse and a first verify pulse of a first program loop from among the plurality of program loops, counting a first off cell count by using an output based on the first verify pulse, determining a first verify skip period using the first off cell count, applying an N-th program pulse and a plurality of verify pulses in response to an end of the first verify skip period, counting a second off cell count by using an output based on the plurality of verify pulses, and determining a second verify skip period using the second off cell count.

公开(公告)号：US20240379164A1

公开(公告)日：2024-11-14

申请号：US18602636

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosul SHIN ,  Sungwon Yun ,  Hyunkook Park ,  Hyunjun Yoon

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

Abstract: A method of programming data in a nonvolatile memory device includes setting a state ordering to a first state ordering, the state ordering representing a relationship between a plurality of states and data values of multi-bit data, performing, based on the first state ordering, a program operation on target memory cells of the plurality of memory cells, swapping the state ordering from the first state ordering to a second state ordering different from the first state ordering, performing, based on the second state ordering, the program operation on the target memory cells, re-swapping the state ordering from the second state ordering to the first state ordering, and performing, based on the first state ordering, the program operation on the target memory cells. Each memory cell of a plurality of memory cells of the nonvolatile memory device is programmed to have one of the plurality of states.

公开(公告)号：US20220068322A1

公开(公告)日：2022-03-03

申请号：US17222024

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C16/34

Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

公开(公告)号：US12277976B2

公开(公告)日：2025-04-15

申请号：US17941570

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun Yoon ,  Jinwoo Park

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/34

Abstract: Provided are a non-volatile memory device, a storage device including the same, and a method of performing a programming operation on the same. The method includes performing a program operation including applying a desired first program voltage to a selected word line of the memory device, the selected word line including a plurality of memory cells, performing a verification operation including sensing a first sensing value corresponding to an output of the selected word line based on a first verify voltage, and counting a number of on-cells of the selected word line based on the first sensing value to determine a first count value, determining whether a first program state of the selected word line has been verified based on the first count value and at least one reference value, and setting a second program voltage based on results of the determining whether the first program state has been verified.

公开(公告)号：US12073909B2

公开(公告)日：2024-08-27

申请号：US18085963

申请日：2022-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C16/34

CPC classification number: G11C7/065 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/3404

Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

公开(公告)号：US11989082B2

公开(公告)日：2024-05-21

申请号：US18057328

申请日：2022-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejin Kim ,  Hyunjun Yoon

IPC: G06F11/07 ,  G06F12/0882 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: G06F11/0778 ,  G06F11/0757 ,  G06F12/0882 ,  G06F13/1673 ,  G11C7/1039 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4093

Abstract: A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.

公开(公告)号：US11869582B2

公开(公告)日：2024-01-09

申请号：US17510828

申请日：2021-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoon Park ,  Sungwon Yun ,  Hyunjun Yoon ,  Wontaeck Jung

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A method of operating a memory device that performs a plurality of program loops for a plurality of memory cells includes applying a first program pulse and a first verify pulse of a first program loop from among the plurality of program loops, counting a first off cell count by using an output based on the first verify pulse, determining a first verify skip period using the first off cell count, applying an N-th program pulse and a plurality of verify pulses in response to an end of the first verify skip period, counting a second off cell count by using an output based on the plurality of verify pulses, and determining a second verify skip period using the second off cell count.