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公开(公告)号:US20230361121A1
公开(公告)日:2023-11-09
申请号:US18353214
申请日:2023-07-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongsoo LEE , Wonkeun CHUNG , Hoonjoo NA , Suyoung BAE , Jaeyeol SONG , Jonghan LEE , HyungSuk JUNG , Sangjin HYUN
IPC: H01L27/092 , H01L29/786 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L29/423
CPC classification number: H01L27/0922 , H01L29/78696 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/42392
Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.
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公开(公告)号:US20210358910A1
公开(公告)日:2021-11-18
申请号:US17384920
申请日:2021-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongsoo LEE , Wonkeun CHUNG , Hoonjoo NA , Suyoung BAE , Jaeyeol SONG , Jonghan LEE , HyungSuk JUNG , Sangjin HYUN
IPC: H01L27/092 , H01L29/786 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L29/423
Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.
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公开(公告)号:US20240030305A1
公开(公告)日:2024-01-25
申请号:US18199133
申请日:2023-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaehyun LEE , Jonghan LEE , Jonghoon BAEK , Taegon KIM , Yujin JUNG
IPC: H01L29/423 , H01L29/06 , H01L29/775 , H01L29/786
CPC classification number: H01L29/42392 , H01L29/0673 , H01L29/775 , H01L29/78696
Abstract: The present disclosure provides for semiconductor devices including field effect transistors. In some embodiments, the semiconductor device includes active structures extending in a first direction on a substrate, an isolation pattern formed in a trench between the active structures, gate structures extending in a second direction across the active structures, a cutting insulation pattern formed between end portions of the gate structures in the second direction, and a lower impurity region at an upper portion of the isolation pattern. A first shape of a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed under the uppermost surface of the isolation pattern. The gate structures are formed on the active structures and the isolation pattern. The lower impurity region contacts at least a portion of the cutting insulation pattern.
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公开(公告)号:US20220223592A1
公开(公告)日:2022-07-14
申请号:US17705565
申请日:2022-03-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seonghwa PARK , Hongbae PARK , Jaehyun LEE , Jonghan LEE , Dabok JEONG , Minseok JO
IPC: H01L27/088 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/308
Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern and the second gate pattern being spaced apart from each other, and a separation pattern that separates the first gate pattern and the second gate pattern from each other. The first gate pattern includes a first high-k dielectric pattern and a first metal-containing pattern on the first high-k dielectric pattern, the first metal-containing pattern covering a sidewall of the first high-k dielectric pattern. The second gate pattern includes a second high-k dielectric pattern and a second metal-containing pattern on the second high-k dielectric pattern, and the separation pattern is in direct contact with the first metal-containing pattern and spaced apart from the first high-k dielectric pattern.
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公开(公告)号:US20170084507A1
公开(公告)日:2017-03-23
申请号:US15273933
申请日:2016-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangyub IE , Minwoo SONG , Jonghan LEE , Hyungsuk JUNG , Hyeri HONG
IPC: H01L21/66 , H01L29/49 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/8234
CPC classification number: H01L22/34 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L22/14 , H01L27/0886 , H01L29/0847 , H01L29/42364 , H01L29/4966 , H01L29/66545 , H01L29/7848
Abstract: A method of fabricating a semiconductor device includes forming first and second fin patterns in an active region and in a measurement region of a substrate, respectively, the measurement region being different from the active region, forming first and second gate electrodes to cross the first and second fin patterns, respectively, and measuring a contact potential difference (Vcpd) of the second gate electrode to determine a threshold voltage of the first gate electrode based on the measured contact potential difference (Vcpd).
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