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    INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20250107179A1

    公开(公告)日：2025-03-27

    申请号：US18663867

    申请日：2024-05-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Wonkeun CHUNG ,  Geunwoo KIM ,  Wandon KIM ,  Hyoseok CHOI

    IPC: H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: Provided is an integrated circuit device and a method of manufacturing same, the integrated circuit device including: a fin-type active region on a substrate, a pair of insulating spacers on the fin-type active region and the substrate and defining a first space, a gate dielectric film contacting the gate line in the first space, a gate contact plug having a conductive bottom surface contacting a top contact portion of the gate line in the first space, and a capping insulating pattern including an insulating bottom surface, a pair of first insulating sidewalls, and a second insulating sidewall, the insulating bottom surface contacting a local top surface of the gate line in the first space, the pair of first insulating sidewalls contacting the pair of insulating spacers, and the second insulating sidewall contacting the gate contact plug, wherein an insulating top surface of the capping insulating pattern and a conductive top surface of the gate contact plug extend along one plane.

    INTEGRATED CIRCUIT DEVICE
    3.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20250096134A1

    公开(公告)日：2025-03-20

    申请号：US18650288

    申请日：2024-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geunwoo KIM ,  Hyunwoo KANG ,  Mingyu KIM ,  Wandon KIM ,  Wonkeun CHUNG ,  Hyoseok CHOI

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

    Abstract: An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210358910A1

    公开(公告)日：2021-11-18

    申请号：US17384920

    申请日：2021-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsoo LEE ,  Wonkeun CHUNG ,  Hoonjoo NA ,  Suyoung BAE ,  Jaeyeol SONG ,  Jonghan LEE ,  HyungSuk JUNG ,  Sangjin HYUN

    IPC: H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

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