公开(公告)号：US12132159B2

公开(公告)日：2024-10-29

申请号：US17567671

申请日：2022-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Lim ,  Myoungsu Chae ,  Yeonjun Sung ,  Hyongsik Won ,  Joonwoo Jeon ,  Soonwon Jeong

IPC: H01L33/50 ,  H01L33/62 ,  H05K1/11

CPC classification number: H01L33/62 ,  H05K1/111

Abstract: A light-emitting diode (LED) package includes a package substrate, an LED chip disposed on a first surface of the package substrate, and a first external connection pad and a second external connection pad disposed on a second surface of the package substrate opposite the first surface. The first external connection pad includes a first side, a second side, a third side and a fourth side, the first side being parallel to the second side, and the third side being parallel to the fourth side. The first side is spaced farther from a center of the package substrate than the second side. A length of the first side is shorter than a length of the second side.

公开(公告)号：US20220209088A1

公开(公告)日：2022-06-30

申请号：US17533949

申请日：2021-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonwon JEONG ,  Yeonjun Sung ,  Jongho Lim ,  Joonwoo Jeon ,  Hanna Heo ,  Hyongsik Won ,  Sangbok Yun

IPC: H01L33/64 ,  H01L25/075 ,  H01L33/62 ,  H01L25/16

Abstract: A light emitting device package includes a first molding member surrounding a heat dissipation frame, a first electrode frame, and a second electrode frame; a first semiconductor light emitting device on the heat dissipation frame and having first and second pads; a second semiconductor light emitting device on the heat dissipation frame and having first and second pads; a wavelength conversion layer on the first and second semiconductor light emitting structures; a first bonding wire connected to the first pad of the first semiconductor light emitting device and the first electrode frame; a second bonding wire connected to the second pad of the second semiconductor light emitting device and the second electrode frame; and an inter-chip bonding wire connecting the second pad of the first semiconductor light emitting device to the first pad of the second semiconductor light emitting device.

公开(公告)号：US12119437B2

公开(公告)日：2024-10-15

申请号：US17533949

申请日：2021-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonwon Jeong ,  Yeonjun Sung ,  Jongho Lim ,  Joonwoo Jeon ,  Hanna Heo ,  Hyongsik Won ,  Sangbok Yun

IPC: H01L33/62 ,  H01L25/075 ,  H01L25/16 ,  H01L33/64 ,  H01L23/00 ,  H01L33/50

CPC classification number: H01L33/644 ,  H01L25/0753 ,  H01L25/162 ,  H01L33/62 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L33/505 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/49109 ,  H01L2924/12035 ,  H01L2924/12041

Abstract: A light emitting device package includes a first molding member surrounding a heat dissipation frame, a first electrode frame, and a second electrode frame; a first semiconductor light emitting device on the heat dissipation frame and having first and second pads; a second semiconductor light emitting device on the heat dissipation frame and having first and second pads; a wavelength conversion layer on the first and second semiconductor light emitting structures; a first bonding wire connected to the first pad of the first semiconductor light emitting device and the first electrode frame; a second bonding wire connected to the second pad of the second semiconductor light emitting device and the second electrode frame; and an inter-chip bonding wire connecting the second pad of the first semiconductor light emitting device to the first pad of the second semiconductor light emitting device.

公开(公告)号：US12010840B2

公开(公告)日：2024-06-11

申请号：US17013726

申请日：2020-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Leeeun Ku ,  Yuna Lee ,  Sunyoung Kim ,  Kyungjae Park ,  Jonghyun Park ,  Bora Lee ,  Jongho Lim

IPC: H01L27/115 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10

Abstract: A vertical type non-volatile memory device includes a substrate having a cell array area of a block unit and an extension area, a vertical contact disposed in the extension area, a plurality of vertical channel structures provided on the substrate in the cell array area, a plurality of dummy channel structures provided on the substrate in the extension area, and a plurality of gate electrode layers and a plurality of interlayer insulation layers stacked alternately on the substrate. In an electrode pad connected to the vertical contact, dummy channel structures are disposed at both sides of the vertical contact and a horizontal cross-sectional surface of each of the plurality of dummy channel structures has a shape which is longer in one direction.

公开(公告)号：US11456335B2

公开(公告)日：2022-09-27

申请号：US17031037

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Lim ,  Hoosung Cho ,  Hongsoo Kim

IPC: H01L27/24 ,  H01L27/115 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/112 ,  H01L23/48

Abstract: A vertical memory device includes circuit patterns of peripheral circuits on a substrate, the circuit patterns including a lower conductive pattern, cell stack structures over the circuit patterns and spaced apart in a first horizontal direction, wherein each of the cell stack structures includes gate electrodes spaced apart in a vertical direction, a first insulating interlayer covering the cell stack structures and a portion between the cell stack structures, a through via contact passing through the first insulating interlayer between the cell stack structures to contact an upper surface of the lower conductive pattern, at least one dummy through via contact passing through the first insulating interlayer between the cell stack structures and disposed adjacent to the through via contact, and upper wiring on the through via contact.