公开(公告)号：US20240282828A1

公开(公告)日：2024-08-22

申请号：US18238872

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  KYOUNGWOO LEE ,  MINCHAN GWAK ,  Gukhee Kim ,  SANGCHEOL NA ,  Anthony Dongick Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An embodiment provides a semiconductor device including a semiconductor substrate having first and second surfaces opposite each other, a channel pattern disposed on the first surface of the semiconductor substrate; source/drain patterns disposed on the first surface of the semiconductor substrate and disposed at both sides of the channel pattern; first and second etch stop films disposed on the first surface of the semiconductor substrate; a contact electrode electrically connected to the source/drain patterns; a lower wire structure disposed on the second surface of the semiconductor substrate; and a through via that passes through the semiconductor substrate, the first etch stop film, and the second etch stop film to connect the contact electrode and the lower wire structure, wherein the through via includes a first portion contacting the contact electrode and a second portion contacting the first portion and disposed between the first portion and the lower wire structure.

公开(公告)号：US20240095113A1

公开(公告)日：2024-03-21

申请号：US18232442

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAESUN KIM ,  JINHONG PARK ,  HWISOO SO ,  KYOUNGWOO LEE ,  JINHYO JUNG

IPC: G06F11/07 ,  G06F9/38

CPC classification number: G06F11/0751 ,  G06F9/3867

Abstract: A processor includes an instruction pipeline that sequentially processes an original instruction and a duplicate instruction, which is generated by duplicating the original instruction. An original register file stores a result obtained by processing the original instruction in the instruction pipeline within a register of a nth index thereof. A duplicate register file stores a result obtained by processing the duplicate instruction in the instruction pipeline within a register of a nth index thereof. A comparing unit compares the register of the nth index in the original register file with the register of nth index in the duplicate register file and outputs an error detection signal, in response to a control signal.

公开(公告)号：US20160104680A1

公开(公告)日：2016-04-14

申请号：US14974089

申请日：2015-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOJIN JANG ,  KYOUNGWOO LEE

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2224/13

Abstract: A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.

Abstract translation: 提供一种形成半导体器件的金属互连的方法。 该方法包括形成包括开口的低k电介质层; 形成保形地覆盖所述开口的底部表面和内侧壁的阻挡金属图案; 形成露出所述开口中的所述阻挡金属图案的内侧壁的一部分的金属图案; 使用选择性化学气相沉积工艺在金属图案和低k电介质层的顶表面上形成金属覆盖层，其中金属图案上的金属覆盖层的厚度大于金属覆盖层的厚度 在低k电介质层上; 以及通过将金属覆盖层平坦化到低k电介质层的顶表面来形成覆盖金属图案的顶表面的金属覆盖图案。