公开(公告)号：US20220343957A1

公开(公告)日：2022-10-27

申请号：US17526398

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US20240395298A1

公开(公告)日：2024-11-28

申请号：US18794825

申请日：2024-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

公开(公告)号：US10608664B2

公开(公告)日：2020-03-31

申请号：US16240075

申请日：2019-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongsoo Lee ,  Youngchul Cho ,  Kwanghoon Son ,  Byeoungwook Kim

IPC: H04N7/26 ,  H03M7/32 ,  G06N20/00 ,  G06N3/08 ,  H03M13/41 ,  G05B13/00 ,  H03M5/00 ,  G06N7/02 ,  H03M1/12 ,  H03M7/00

Abstract: A data compression method and a data decompression method are provided. The method includes pruning an original data including a plurality of weight parameters, identifying at least one first weight parameter of which at least one first value is not changed by the pruning, among multiple weight parameters included in the pruned original data, and obtaining a first index data including location information of the at least one first weight parameter of which the at least one first value is not changed, identifying at least one second weight parameter of which at least one second value is changed by the pruning, among the multiple weight parameters included in the pruned original data, and substituting the at least one second weight parameter of which the at least one second value is changed with a don't care parameter.

公开(公告)号：US12080379B2

公开(公告)日：2024-09-03

申请号：US17939016

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

公开(公告)号：US11545966B2

公开(公告)日：2023-01-03

申请号：US17224577

申请日：2021-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Choi ,  Wonjoo Jung ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: H03B27/00 ,  H03K5/01

Abstract: An injection locking oscillator (ILO) circuit includes; an injection circuit that receives input signals having a phase difference and provides injection signals respectively corresponding to the input signals based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a poly-phase signal output circuit that provides poly-phased signals having a phase difference between signals fixed to a defined phase difference upon receiving the injection signals from the input terminals.

公开(公告)号：US20220336004A1

公开(公告)日：2022-10-20

申请号：US17508598

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C11/4076 ,  H01L25/065

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US12057156B2

公开(公告)日：2024-08-06

申请号：US18218243

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  H03K5/156 ,  H03K5/12

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US20230343383A1

公开(公告)日：2023-10-26

申请号：US18218243

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C11/4076 ,  G11C7/22 ,  G11C29/02 ,  H03K5/156

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US11699472B2

公开(公告)日：2023-07-11

申请号：US17526398

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US20240356553A1

公开(公告)日：2024-10-24

申请号：US18487448

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mingyu Lee ,  Seungjin Park ,  Doobock Lee ,  Youngchul Cho

IPC: H03K19/0185 ,  H03K3/356 ,  H03K17/22 ,  H03K19/003

CPC classification number: H03K19/018521 ,  H03K3/356113 ,  H03K17/223 ,  H03K19/00384

Abstract: A semiconductor device includes a first power node configured to supply a first power supply voltage, a pull-up circuit electrically connected between the first power node and an output node that is configured to output a signal, and a controller configured to output a pull-up control code to the pull-up circuit. The pull-up circuit includes a plurality of unit circuits electrically connected to each other in parallel between the first power node and the output node, and the plurality of unit circuits include a first unit circuit and a second unit circuit. The number of current paths provided by the first unit circuit between the first power node and the output node is different from the number of current paths provided by the second unit circuit between the first power node and the output node.