公开(公告)号：US20210193230A1

公开(公告)日：2021-06-24

申请号：US16724896

申请日：2019-12-23

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Seungpil Lee ,  Ali Al-Shamma

IPC: G11C16/26 ,  G11C16/04

Abstract: A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.

公开(公告)号：US20190371380A1

公开(公告)日：2019-12-05

申请号：US16000816

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Yadhu Vamshi Vancha ,  James Hart ,  Jeffrey Koon Yee Lee ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yingchang Chen

IPC: G11C8/08 ,  G11C7/12 ,  G11C7/08

Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

公开(公告)号：US09715924B2

公开(公告)日：2017-07-25

申请号：US15299338

申请日：2016-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nima Mokhlesi ,  Ali Al-Shamma

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C5/14 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.

公开(公告)号：US11024392B1

公开(公告)日：2021-06-01

申请号：US16724896

申请日：2019-12-23

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Seungpil Lee ,  Ali Al-Shamma

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56

Abstract: A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.

公开(公告)号：US20200234743A1

公开(公告)日：2020-07-23

申请号：US16251484

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yadhu Vamshi Vancha ,  Ali Al-Shamma ,  Yingchang Chen ,  Jeffrey Lee ,  Tz-Yi Liu

IPC: G11C7/06 ,  G11C11/16

Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

公开(公告)号：US20170117036A1

公开(公告)日：2017-04-27

申请号：US15299357

申请日：2016-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ali Al-Shamma ,  Nima Mokhlesi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3459 ,  G11C16/3481 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/0403 ,  H01L27/11582 ,  H01L28/00

Abstract: A non-volatile storage system includes a plurality of non-volatile memory cells configured to form a monolithic three dimensional memory structure, a plurality of bit lines connected to the memory cells, a plurality of source lines connected to the memory cells, a plurality of bit line drivers connected to the bit lines and a plurality of source line drivers connected to the source lines and the bit lines. The source line drivers apply voltages to the source lines based on bit line voltages.

公开(公告)号：US11031059B2

公开(公告)日：2021-06-08

申请号：US16281699

申请日：2019-02-21

Applicant: SanDisk Technologies LLC

Inventor： Christopher J. Petti ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yoocharn Jeon

IPC: G11C11/16 ,  H01L27/22

Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

公开(公告)号：US10734048B2

公开(公告)日：2020-08-04

申请号：US16000816

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Yadhu Vamshi Vancha ,  James Hart ,  Jeffrey Koon Yee Lee ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yingchang Chen

IPC: G11C8/08 ,  G11C7/08 ,  G11C7/12

Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

公开(公告)号：US20180342273A1

公开(公告)日：2018-11-29

申请号：US15602889

申请日：2017-05-23

Applicant: SanDisk Technologies LLC

Inventor： Ali Al-Shamma ,  Tz-yi Liu

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/02 ,  G11C7/065 ,  G11C7/10 ,  G11C7/22

Abstract: A calibration circuit coupled to a sense amplifier circuit may be configured to determine a response time of the sense amplifier circuit relative to a pulse sequence. Based on the determined response time, the calibration circuit may be configured to set a level of a biasing current to a desired level in order to control the response time of the sense amplifier circuit.

公开(公告)号：US10832770B2

公开(公告)日：2020-11-10

申请号：US16352749

申请日：2019-03-13

Applicant: SanDisk Technologies LLC

Inventor： Ali Al-Shamma ,  Yadhu Vamshi Vancha ,  Jeffrey Lee

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a single pulse memory operation. An electrical source is configured to generate an electrical pulse. A selector for a memory cell is configured to conduct an electrical pulse from an electrical source to a memory cell in response to the electrical pulse exceeding a threshold. A control circuit is configured to maintain at least an operational level for the electrical pulse for a predefined time period to perform an operation on the memory cell.