公开(公告)号：US09184299B2

公开(公告)日：2015-11-10

申请号：US14207750

申请日：2014-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC: H01L29/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Abstract translation: 对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤， 其中形成沟道区。 将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，将氧化物半导体层和栅极绝缘层的厚度设定为15nm〜30nm，包括20nm〜50nm， 或分别为15nm〜100nm，10nm〜20nm。 因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

公开(公告)号：US10411102B2

公开(公告)日：2019-09-10

申请号：US15841891

申请日：2017-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L21/02 ,  H01L27/12 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786 ,  H01L51/05 ,  H01L51/10

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

公开(公告)号：US09543445B2

公开(公告)日：2017-01-10

申请号：US14666761

申请日：2015-03-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L29/1033 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/78696

Abstract: A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈r/d is greater than or equal to 0.08 (nm−1) and less than or equal to 7.9 (nm−1) when the relative permittivity of a material used for the gate insulating layer is ∈r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.

Abstract translation: 一种半导体器件，包括氧化物半导体层，与氧化物半导体层电连接的源电极和漏电极，覆盖氧化物半导体层的栅绝缘层，源电极和漏电极以及栅电极 提供栅极绝缘层。 氧化物半导体层的厚度大于或等于1nm且小于或等于10nm。 当栅极绝缘层用的材料的相对介电常数为（0.65）〜（0.85））时，栅极绝缘层满足关系式∈r/ d大于等于0.08（nm-1）且小于等于7.9（nm-1） ∈r，栅极绝缘层的厚度为d。 源电极和漏电极之间的距离大于或等于10nm且小于或等于1μm。

公开(公告)号：US09006025B2

公开(公告)日：2015-04-14

申请号：US14151046

申请日：2014-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/1033 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/78696

Abstract: A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈r/d is greater than or equal to 0.08 (nm−1) and less than or equal to 7.9 (nm−1) when the relative permittivity of a material used for the gate insulating layer is ∈r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.

Abstract translation: 一种半导体器件，包括氧化物半导体层，与氧化物半导体层电连接的源电极和漏电极，覆盖氧化物半导体层的栅绝缘层，源电极和漏电极以及栅电极 提供栅极绝缘层。 氧化物半导体层的厚度大于或等于1nm且小于或等于10nm。 当栅极绝缘层用的材料的相对介电常数为（0.65）〜（0.85））时，栅极绝缘层满足关系式∈r/ d大于等于0.08（nm-1）且小于等于7.9（nm-1） ∈r，栅极绝缘层的厚度为d。 源电极和漏电极之间的距离大于或等于10nm且小于或等于1μm。

公开(公告)号：US20140327002A1

公开(公告)日：2014-11-06

申请号：US14337297

申请日：2014-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Kawae

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0255 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/861 ,  H02H9/044 ,  Y10S257/91

Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, The work function φms of a source electrode in contact with the oxide semiconductor, the work function φmd of a drain electrode in contact with the oxide semiconductor, and electron affinity χ of the oxide semiconductor satisfy φms≦χ

Abstract translation: 提供了使用氧化物半导体的非线性元件，例如二极管，并且整流性能良好。 在包含氢浓度小于或等于5×1019 / cm3的氧化物半导体的薄膜晶体管中，与氧化物半导体接触的源电极的功函数＆amp; ms， 与氧化物半导体接触的漏极，氧化物半导体的电子亲和力χ满足＆lt; ms＆nlE;χ＆phgr; md。 通过电连接薄膜晶体管的栅电极和漏电极，可以实现具有更好的整流特性的非线性元件。

公开(公告)号：US08803146B2

公开(公告)日：2014-08-12

申请号：US13763874

申请日：2013-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L21/00

CPC classification number: H01L29/41733 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0508 ,  H01L51/0512 ,  H01L51/0545 ,  H01L51/105

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract translation: 下栅极薄膜晶体管中的源电极和漏电极之间可能发生的电场浓度被放宽并且抑制了开关特性的劣化的结构及其制造方法。 制造在源电极和漏电极上设置氧化物半导体层的底栅薄膜晶体管，与氧化物半导体层接触的源电极的侧表面的角度和角度;角度和角度; 与氧化物半导体层接触的漏电极的侧面的两个面积分别被设定为大于或等于20°且小于90°，​​使得从上边缘到下边缘的距离 每个电极的侧表面增加。

公开(公告)号：US11239332B2

公开(公告)日：2022-02-01

申请号：US16846569

申请日：2020-04-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/786 ,  H01L51/05 ,  H01L51/10 ,  H01L27/12 ,  H01L21/02

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

公开(公告)号：US10665684B2

公开(公告)日：2020-05-26

申请号：US16180580

申请日：2018-11-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/417 ,  H01L27/12 ,  H01L51/05 ,  H01L51/10 ,  H01L21/02

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

公开(公告)号：US09293545B2

公开(公告)日：2016-03-22

申请号：US14451680

申请日：2014-08-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L29/786 ,  H01L29/417 ,  H01L51/05 ,  H01L29/49 ,  H01L51/10 ,  H01L27/12 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/41733 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0508 ,  H01L51/0512 ,  H01L51/0545 ,  H01L51/105

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract translation: 下栅极薄膜晶体管中的源电极和漏电极之间可能发生的电场浓度被放宽并且抑制了开关特性的劣化的结构及其制造方法。 制造在源电极和漏电极上设置氧化物半导体层的底栅薄膜晶体管，与氧化物半导体层接触的源电极的侧表面的角度和角度;角度和角度; 与氧化物半导体层接触的漏电极的侧面的两个面积分别被设定为大于或等于20°且小于90°，​​使得从上边缘到下边缘的距离 每个电极的侧表面增加。

公开(公告)号：US20140191232A1

公开(公告)日：2014-07-10

申请号：US14207750

申请日：2014-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC: H01L29/786

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Abstract translation: 对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤， 其中形成沟道区。 将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，将氧化物半导体层和栅极绝缘层的厚度设定为15nm〜30nm，包括20nm〜50nm， 或分别为15nm〜100nm，10nm〜20nm。 因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。