公开(公告)号：US20170323892A1

公开(公告)日：2017-11-09

申请号：US15497752

申请日：2017-04-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami ENDO

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/108 ,  H01L27/10847 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10867 ,  H01L27/1156 ,  H01L29/7869

Abstract: A memory device which stores a large amount of data is provided. The memory device includes a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and first to third wirings. The first transistor includes an oxide semiconductor in a channel formation region, the second transistor includes silicon in a channel formation region, and the third transistor includes silicon in a channel formation region. The first capacitor is provided in the same layer as the first transistor. A region of the second capacitor and a region of the first capacitor overlap with each other. The thickness of a dielectric of the second capacitor is preferably larger than the thickness of a dielectric of the first capacitor.

公开(公告)号：US20250133906A1

公开(公告)日：2025-04-24

申请号：US18574564

申请日：2022-07-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hidetomo KOBAYASHI ,  Yuki OKAMOTO ,  Toshihiko SAITO ,  Tatsuya ONUKI ,  Hidekazu MIYAIRI ,  Ryo TAGASHIRA ,  Kazuko YAMAWAKI ,  Masami ENDO

IPC: H10K59/121 ,  G09G3/3233 ,  H10K59/131

Abstract: A semiconductor device with high manufacturing yield is provided. The semiconductor device includes a plurality of subpixels. Each of the subpixels includes a first transistor, a second transistor, a first capacitor to a third capacitor, a first insulating layer, and a wiring. Each of the first capacitor to the third capacitor includes a first conductive layer, a second conductive layer, and a second insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer is provided over the first transistor and the second transistor. The first conductive layers of the first capacitor to the third capacitor and the wiring are each provided over the first insulating layer. In a top view, the proportion of the total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to the area of the subpixel is greater than or equal to 15 percent. The area of the first conductive layer of the second capacitor and the area of the first conductive layer of the third capacitor are each greater than or equal to twice the area of the first conductive layer of the first capacitor.

公开(公告)号：US20160225774A1

公开(公告)日：2016-08-04

申请号：US15096368

申请日：2016-04-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro OHMARU ,  Masami ENDO

IPC: H01L27/105 ,  H01L27/06 ,  H01L23/522 ,  H01L29/786

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C11/24 ,  G11C14/0009 ,  G11C19/184 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10897 ,  H01L28/20 ,  H01L28/40 ,  H01L29/24 ,  H01L29/26 ,  H01L29/7869 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

公开(公告)号：US20170062433A1

公开(公告)日：2017-03-02

申请号：US15238933

申请日：2016-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Masami ENDO

IPC: H01L27/105 ,  H01L29/66 ,  H01L29/792 ,  H01L29/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device capable of retaining data for a long time is provided. A semiconductor device includes a first transistor including a first insulator, a first oxide semiconductor, a first gate, and a second gate; a second transistor including a second oxide semiconductor, a third gate, and a fourth gate; and a node. The first gate and the second gate overlap with each other with the first oxide semiconductor therebetween. The third gate and the fourth gate overlap with each other with the second oxide semiconductor therebetween. The first oxide semiconductor and the second gate overlap with each other with the first insulator therebetween. One of a source and a drain of the first transistor, the first gate, and the fourth gate are electrically connected to the node. The first insulator is configured to charges.

Abstract translation: 提供能够长时间保留数据的半导体器件。 半导体器件包括：第一晶体管，包括第一绝缘体，第一氧化物半导体，第一栅极和第二栅极; 第二晶体管，包括第二氧化物半导体，第三栅极和第四栅极; 和一个节点。 第一栅极和第二栅极彼此重叠，其间具有第一氧化物半导体。 第三栅极和第四栅极彼此重叠，其间具有第二氧化物半导体。 第一氧化物半导体和第二栅极彼此重叠，其间具有第一绝缘体。 第一晶体管，第一栅极和第四栅极的源极和漏极之一电连接到节点。 第一绝缘体配置成充电。

公开(公告)号：US20170032825A1

公开(公告)日：2017-02-02

申请号：US15291145

申请日：2016-10-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami ENDO

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/12 ,  G11C14/0054 ,  G11C16/0441 ,  G11C19/184 ,  G11C19/28

Abstract: A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.

Abstract translation: 提供具有新颖结构的存储元件和包括存储元件的信号处理电路。 包括包括第一晶体管和第二晶体管的第一电路和包括第三晶体管和第四晶体管的第二电路。 分别对应于输入信号的第一信号电位和第二信号电位经由导通状态的第一晶体管分别输入到第二晶体管的栅极，并经由第三晶体管的导通 州。 之后，第一晶体管和第三晶体管截止。 使用第二晶体管和第四晶体管的状态来读出输入信号。 包括其中形成沟道的氧化物半导体的晶体管可以用于第一晶体管和第三晶体管。

公开(公告)号：US20170263609A1

公开(公告)日：2017-09-14

申请号：US15469721

申请日：2017-03-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami ENDO

IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1052 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

Abstract: To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.

公开(公告)号：US20150171117A1

公开(公告)日：2015-06-18

申请号：US14632282

申请日：2015-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami ENDO ,  Kazuaki OHSHIMA

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/786

CPC classification number: H01L27/1225 ,  G09G3/3648 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2320/0214 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/7869

Abstract: A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.

Abstract translation: 公开了能够控制并保持晶体管的阈值电压达到最佳水平的半导体电路及其驱动方法。 还提供了存储装置，显示装置或包括半导体电路的电子装置。 该半导体电路包括一个二极管和一个设置在一个节点上的第一电容器，待控制的晶体管通过其后门连接到该节点上。 这种结构允许将期望的电压施加到背栅极，使得晶体管的阈值电压被控制在最佳水平并且可以保持很长时间。 可选地提供与二极管并联连接的第二电容器，使得可以暂时改变节点的电压。