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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20230027616A1

    公开(公告)日：2023-01-26

    申请号：US17945800

    申请日：2022-09-15

    Applicant: Socionext Inc.

    Inventor： Toshio HINO

    IPC: H01L27/02 ,  H01L23/528

    Abstract: A semiconductor integrated circuit device includes a clock buffer cell that is a standard cell transmitting a clock signal. The clock buffer cell has an input terminal and an output terminal. A first metal interconnect including the output terminal is located in a layer above a second metal interconnect including the input terminal and greater in width than the second metal interconnect.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20210028191A1

    公开(公告)日：2021-01-28

    申请号：US17065875

    申请日：2020-10-08

    Applicant: SOCIONEXT INC.

    Inventor： Toshio HINO ,  Junji IWAHORI

    IPC: H01L27/118 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02

    Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    5.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20190123063A1

    公开(公告)日：2019-04-25

    申请号：US16228319

    申请日：2018-12-20

    Applicant: SOCIONEXT INC.

    Inventor： Toshio HINO ,  Junji IWAHORI

    IPC: H01L27/118 ,  H01L27/02

    Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    6.
    发明公开
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240332304A1

    公开(公告)日：2024-10-03

    申请号：US18738947

    申请日：2024-06-10

    Applicant: Socionext Inc.

    Inventor： Hideyuki KOMURO ,  Toshio HINO ,  Junji IWAHORI

    IPC: H01L27/118

    CPC classification number: H01L27/11807 ,  H01L2027/11881

    Abstract: First and second semiconductor chips are stacked one upon the other with the back face of the first semiconductor chip opposed to the principal face of the second semiconductor chip. The first semiconductor chip includes: first and second power lines formed in a buried interconnect layer, extending in the X direction, and adjoining each other in the Y direction; first and second contacts provided between the first and second power lines and the chip back face; and a third contact provided between a signal line and the chip back face. The third contact is located between the first and second power lines in the Y direction, and at a position different from the positions of the first and second contacts in the X direction, in planar view.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    9.
    发明公开
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240304629A1

    公开(公告)日：2024-09-12

    申请号：US18668988

    申请日：2024-05-20

    Applicant: Socionext Inc.

    Inventor： Toshio HINO

    IPC: H01L27/092 ,  H01L23/528 ,  H01L27/02

    CPC classification number: H01L27/0928 ,  H01L23/5286 ,  H01L27/0207

    Abstract: In a standard cell of a semiconductor integrated circuit device, a metal interconnect corresponding to an input node is connected to the gates of first and second transistors, and a metal interconnect corresponding to an output node is connected to the drains of third and fourth transistors. A metal interconnect corresponding to an intermediate node is connected to a gate interconnect corresponding to the gates of the third and fourth transistors through a gate contact. The gate contact is placed at a position overlapping the third transistor in planar view.

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