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公开(公告)号：US20180012935A1
公开(公告)日：2018-01-11
申请号：US15694463
申请日：2017-09-01
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L27/2436 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1666
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US11031550B2
公开(公告)日：2021-06-08
申请号：US16457855
申请日：2019-06-28
Inventor： Philippe Boivin , Simon Jeannot
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US20160380030A1
公开(公告)日：2016-12-29
申请号：US14970347
申请日：2015-12-15
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L27/2436 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1666
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
Abstract translation: 本公开涉及一种形成在晶片中的存储单元，其包括被第一绝缘层覆盖的半导体衬底，绝缘层被由半导体制成的有源层覆盖，所述存储单元包括具有控制栅极和第一绝缘层的选择晶体管 所述导电端子连接到可变电阻元件，所述栅极形成在所述有源层上并具有被第二绝缘层覆盖的侧面，所述可变电阻元件由可变电阻材料层形成，所述可变电阻材料层沉积在侧向 有源层的沿着栅极的侧面通过有源层形成的第一沟槽的侧面，沟槽导体形成在第一沟槽中，抵抗可变电阻材料层的侧面。
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公开(公告)号：US10707270B2
公开(公告)日：2020-07-07
申请号：US16357152
申请日：2019-03-18
Inventor： Philippe Boivin , Simon Jeannot
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US09735353B2
公开(公告)日：2017-08-15
申请号：US15098025
申请日：2016-04-13
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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Patent Agency Ranking
公开(公告)号：US20160380190A1
公开(公告)日：2016-12-29
申请号：US15098025
申请日：2016-04-13
Inventor： Philippe Boivin , Simon Jeannot
IPC: H01L45/00
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
Abstract translation: 存储单元包括具有控制栅极的选择晶体管和连接到可变电阻元件的第一导电端子。 存储单元形成在包括被第一绝缘层覆盖的半导体衬底的晶片中，绝缘层被由半导体制成的有源层覆盖。 栅极形成在有源层上，并具有用第二绝缘层覆盖的侧面。 可变电阻元件包括覆盖有源层的横向侧面的第一层，该沟槽沿着栅极的侧面通过有源层形成并且到达第一绝缘层的沟槽，以及由可变电阻材料制成的第二层 。
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公开(公告)号：US10482957B2
公开(公告)日：2019-11-19
申请号：US15978003
申请日：2018-05-11
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe Boivin , Simon Jeannot , Olivier Weber
Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.
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公开(公告)号：US10283563B2
公开(公告)日：2019-05-07
申请号：US15694463
申请日：2017-09-01
Inventor： Philippe Boivin , Simon Jeannot
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US11957067B2
公开(公告)日：2024-04-09
申请号：US17328917
申请日：2021-05-24
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H10N70/231 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/061 , H10N70/253 , H10N70/823 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/8828 , G11C13/0004 , G11C2213/79 , G11C2213/82
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US20170317275A1
公开(公告)日：2017-11-02
申请号：US15654405
申请日：2017-07-19
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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