公开(公告)号：US20190019745A1

公开(公告)日：2019-01-17

申请号：US16136709

申请日：2018-09-20

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Ian Harvey Arellano ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31

Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

公开(公告)号：US11552007B2

公开(公告)日：2023-01-10

申请号：US17185742

申请日：2021-02-25

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US20180190576A1

公开(公告)日：2018-07-05

申请号：US15399234

申请日：2017-01-05

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49548 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US09953933B1

公开(公告)日：2018-04-24

申请号：US15474904

申请日：2017-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Rennier Rodriguez ,  Ela Mia Cadag

IPC: H01L23/552 ,  H01L23/00 ,  B32B7/12 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/552 ,  B32B7/12 ,  B32B2457/14 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48229 ,  H01L2224/48992 ,  H01L2924/15311 ,  H01L2924/3025

Abstract: A semiconductor package includes a substrate, a die, an insulating die attach film, a dummy die, a conductive layer, and an electrically conductive molding compound or encapsulant. The first surface of the substrate includes a plurality of internal leads, and the second surface of the substrate includes a plurality of external electrically conductive pads and an electrically conductive ground terminal. A non-conductive flow over wire die attach film is placed to surround and encase the die. The dummy die overlies the die and a conductive layer overlies the dummy die. The electrically conductive molding compound is formed to encase the various components of the semiconductor device. The electrically conductive molding compound is electrically coupled to the electrically conductive ground terminal and the conductive layer forming an EMI shield for the die in the package.

公开(公告)号：US09842794B2

公开(公告)日：2017-12-12

申请号：US14945291

申请日：2015-11-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia Cadag ,  Jefferson Talledo

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81002 ,  H01L2224/81986 ,  H01L2224/83002 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2924/00

Abstract: One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.

公开(公告)号：US10957634B2

公开(公告)日：2021-03-23

申请号：US16800923

申请日：2020-02-25

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US10910295B2

公开(公告)日：2021-02-02

申请号：US16712789

申请日：2019-12-12

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Ernesto Antilano, Jr. ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78

Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.

公开(公告)号：US10903172B2

公开(公告)日：2021-01-26

申请号：US16698727

申请日：2019-11-27

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Lester Joseph Belalo ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.

公开(公告)号：US10541196B2

公开(公告)日：2020-01-21

申请号：US16107807

申请日：2018-08-21

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Ernesto Antilano, Jr. ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.

公开(公告)号：US10079198B1

公开(公告)日：2018-09-18

申请号：US15610088

申请日：2017-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Ernesto Antilano, Jr. ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.