公开(公告)号：US20180061781A1

公开(公告)日：2018-03-01

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L21/311 ,  H01L21/768 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US20130286540A1

公开(公告)日：2013-10-31

申请号：US13803619

申请日：2013-03-14

Applicant: NXP B.V. (Dutch Corporation) ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Farcy ,  Maryline Thomas ,  Joaquin Torres ,  Sonarith Chhun ,  Laurent-Georges Gosset

IPC: H01G4/005

CPC classification number: H01G4/005 ,  H01G4/008 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

Abstract: A method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.

Abstract translation: 一种形成金属 - 绝缘体 - 金属电容器的方法，其具有由电介质层隔开的顶板和底板，所述顶板和底板中的一个具有延伸到顶板和底板中的另一个中的相应空腔中的至少一个突起， 方法包括在基底表面上生长一个或多个纳米纤维的步骤。

公开(公告)号：US11183468B2

公开(公告)日：2021-11-23

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/64 ,  H01L23/58 ,  H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US12087708B2

公开(公告)日：2024-09-10

申请号：US17451718

申请日：2021-10-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoit Froment

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/64 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565 ,  H01L23/293

Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.