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公开(公告)号：US20220199632A1
公开(公告)日：2022-06-23
申请号：US17540029
申请日：2021-12-01
Inventor： Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
IPC: H01L27/112
Abstract: The present description concerns a ROM including at least one first rewritable memory cell.
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公开(公告)号：US20180277496A1
公开(公告)日：2018-09-27
申请号：US15784883
申请日：2017-10-16
Inventor： Mathieu Lisart , Raul Andres Bianchi , Benoit Froment
IPC: H01L23/00 , H01L27/088 , H01L23/528 , H03K17/14 , H01L21/8234 , H01L21/265 , H01L21/266 , H01L21/3205 , G06F9/44
Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
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公开(公告)号：US20180233460A1
公开(公告)日：2018-08-16
申请号：US15788611
申请日：2017-10-19
Inventor： Mathieu Lisart , Benoit Froment
IPC: H01L23/00 , H01L23/528 , H01L23/522 , G01R31/02
CPC classification number: H01L23/573 , G01R31/028 , H01L23/5223 , H01L23/5286 , H01L23/576 , H01L23/642 , H01L25/16
Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.
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公开(公告)号：US20210377058A1
公开(公告)日：2021-12-02
申请号：US17329609
申请日：2021-05-25
Inventor： Benoit Froment , Jean-Marc Voisin
IPC: H04L9/32 , H03K19/003
Abstract: An integrated physical unclonable function device includes at least one reference capacitor and a number of comparison capacitors. A capacitance determination circuit operates to determine a capacitance of the at least one reference capacitor and a capacitance of each comparison capacitor. The determined capacitances of the comparison capacitors are then compared to the determined capacitance of the reference capacitor by a comparison circuit. A digital word is then generated with bit values indicative of a result of the comparisons made by the comparison circuit.
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公开(公告)号：US12063775B2
公开(公告)日：2024-08-13
申请号：US18484906
申请日：2023-10-11
Inventor： Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
CPC classification number: H10B20/367 , G11C16/0466 , H01L23/57
Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.
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Patent Agency Ranking
公开(公告)号：US20240040781A1
公开(公告)日：2024-02-01
申请号：US18484906
申请日：2023-10-11
Inventor： Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
IPC: H10B20/00
CPC classification number: H10B20/367 , H01L23/57
Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.
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公开(公告)号：US10754618B2
公开(公告)日：2020-08-25
申请号：US16035798
申请日：2018-07-16
Inventor： Benoit Froment , Sebastien Petitdidier , Mathieu Lisart , Jean-Marc Voisin
IPC: G06F7/58 , H01L21/768 , G06F21/70 , H04L9/08
Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
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公开(公告)号：US20190034168A1
公开(公告)日：2019-01-31
申请号：US16035798
申请日：2018-07-16
Inventor： Benoit Froment , Sebastien Petitdidier , Mathieu Lisart , Jean-Marc Voisin
IPC: G06F7/58 , G06F21/70 , H01L21/768
CPC classification number: G06F7/588 , G06F21/70 , H01L21/76829 , H04L9/0866
Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
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公开(公告)号：US12087708B2
公开(公告)日：2024-09-10
申请号：US17451718
申请日：2021-10-21
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sebastien Petitdidier , Nicolas Hotellier , Raul Andres Bianchi , Alexis Farcy , Benoit Froment
IPC: H01L23/00 , H01L21/311 , H01L21/768 , H01L23/29 , H01L23/31 , H01L23/48 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/58 , H01L23/64 , H03K3/3565
CPC classification number: H01L23/576 , H01L21/31111 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/291 , H01L23/3171 , H01L23/481 , H01L23/49855 , H01L23/5226 , H01L23/528 , H01L23/57 , H01L23/573 , H01L23/585 , H01L23/642 , H03K3/3565 , H01L23/293
Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.
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公开(公告)号：US11818883B2
公开(公告)日：2023-11-14
申请号：US17540029
申请日：2021-12-01
Inventor： Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
CPC classification number: H10B20/367 , G11C16/0466 , H01L23/57
Abstract: The present description concerns a ROM including at least one first rewritable memory cell.
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