公开(公告)号：US20180061781A1

公开(公告)日：2018-03-01

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L21/311 ,  H01L21/768 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US11183468B2

公开(公告)日：2021-11-23

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/64 ,  H01L23/58 ,  H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US20180247874A1

公开(公告)日：2018-08-30

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01C7/12 ,  H01L27/08 ,  H01L49/02 ,  H01L21/74

CPC classification number: H01L21/823493 ,  H01C7/126 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/765 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/8605

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US10354926B2

公开(公告)日：2019-07-16

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/74 ,  H01L27/08 ,  H01L49/02 ,  H01C7/12 ,  H01L21/765 ,  H01L29/8605 ,  H01L23/522 ,  H01L29/06

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.