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公开(公告)号：US10075166B2
公开(公告)日：2018-09-11
申请号：US15361708
申请日：2016-11-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Albert Martinez , Michel Agoyan , Jean Nicolai
IPC: H03K19/003 , H03K5/14 , H03K19/20 , H03L3/00
CPC classification number: H03K19/003 , H03K3/84 , H03K5/14 , H03K19/20 , H03L3/00
Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.
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公开(公告)号：US20170324409A1
公开(公告)日：2017-11-09
申请号：US15361708
申请日：2016-11-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Albert Martinez , Michel Agoyan , Jean Nicolai
IPC: H03K19/003 , H03K5/14 , H03K19/20 , H03L3/00
CPC classification number: H03K19/003 , H03K3/84 , H03K5/14 , H03K19/20 , H03L3/00
Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.
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公开(公告)号：US20170324403A1
公开(公告)日：2017-11-09
申请号：US15358245
申请日：2016-11-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jean Nicolai , Albert Martinez
IPC: H03K3/84 , H03K5/06 , H03K19/003 , H03K21/02
CPC classification number: H03K3/84 , H03K5/06 , H03K19/00323 , H03K21/023 , H03K23/004
Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.
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4.发明申请ELECTRICALLY ACTIVATABLE INTEGRATED MECHANICAL ANTI-ROLLBACK DEVICE WITH ONE OR MORE POSITIONS 有权具有一个或多个位置的电动可激活的机械防反转装置公开(公告)号：US20130250531A1
公开(公告)日：2013-09-26
申请号：US13765064
申请日：2013-02-12
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Albert Martinez , Pascal Fornara
CPC classification number: H05K1/02 , H01G5/04 , H01G5/16 , H01H1/0036 , H01H59/0009 , H05K3/30 , Y10T29/49155
Abstract: A thermally deformable assembly is formed in an integrated-circuit metallization level. The physical behavior of the metal forming the assembly brings the assembly into contact with a stop-forming body when subjected to a temperature change caused by a current flow. A natural rollback to the initial configuration in which the assembly is a certain distance away from the body is prevented. The state or configuration of the assembly is determined by a capacitive reader.
Abstract translation: 热变形组件形成在集成电路金属化层中。 形成组件的金属的物理行为使得组件在受到由电流引起的温度变化时与停止成形体接触。 防止组装距离身体一定距离的初始构造的自然回滚。 组件的状态或配置由电容式读取器确定。
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公开(公告)号：US12019510B2
公开(公告)日：2024-06-25
申请号：US17684198
申请日：2022-03-01
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Albert Martinez , Patrick Haddad
Abstract: The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.
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Patent Agency Ranking
公开(公告)号：US10659020B2
公开(公告)日：2020-05-19
申请号：US16271077
申请日：2019-02-08
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jean Nicolai , Albert Martinez
Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.
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公开(公告)号：US10243543B2
公开(公告)日：2019-03-26
申请号：US15358245
申请日：2016-11-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jean Nicolai , Albert Martinez
Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.
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公开(公告)号：US10162728B2
公开(公告)日：2018-12-25
申请号：US15222368
申请日：2016-07-28
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Albert Martinez
Abstract: A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.
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公开(公告)号：US20170324405A1
公开(公告)日：2017-11-09
申请号：US15361594
申请日：2016-11-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Albert Martinez , Michel Agoyan
IPC: H03K17/00 , H03K19/003 , H03K5/159
CPC classification number: H03K17/005 , G06F7/58 , H03K3/84 , H03K5/159 , H03K19/003 , H03K19/1737
Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.
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公开(公告)号：US11023566B2
公开(公告)日：2021-06-01
申请号：US16150810
申请日：2018-10-03
Inventor： Stefano Lunghi , Albert Martinez
IPC: H04L29/00 , G06F21/12 , G06F12/14 , G06F21/72 , G06F21/79 , G06F9/445 , G06F21/14 , G06F21/60 , G06F21/74 , H04L9/06
Abstract: An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.
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