公开(公告)号：US20240364340A1

公开(公告)日：2024-10-31

申请号：US18627941

申请日：2024-04-05

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Kailash KUMAR

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: A level shifter having current boosting stages is provided. The level shifter includes a level shifting stage including a plurality of transistors and first and second nodes. The level shifting stage is configured to transfer a first signal of a first voltage domain to a second signal of a second voltage domain. A plurality of current boosting stages are associated with the transistors, respectively. A first current boosting stage provides a first boosting stage current path to support a first level shifter current path of a first transistor of the plurality of transistors in response to: a first supply voltage of the first voltage domain being greater than a second supply voltage of the second voltage domain, the first signal having a first logical state and the first node having a logical state reflecting that the first signal has a second logical state different from the first logical state.

公开(公告)号：US20250117350A1

公开(公告)日：2025-04-10

申请号：US18788862

申请日：2024-07-30

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Paras GARG ,  Sandeep KAUSHIK ,  Adarsh Kumar SINGH

IPC: G06F13/40 ,  G06F13/42 ,  H03K17/687

Abstract: Systems, apparatuses, and methods for serial peripheral interfaces are provided, particularly for PVT compensated serial peripheral interfaces with slow transition serial interface IO transmitter with reduced delay. The serial peripheral interfaces may include driver circuitry, pre-driver circuitry, PVT compensated current sink circuitry, and PVT compensated current source circuit. The PVT compensated current sink circuitry and PVT compensated current source circuit may generate and transmit signals compensating for PVT to the pre-driver circuitry, which may generate and transmit signals controlling IO data signals generated by the driver circuitry. The IO data signals generated may be compensated for process, voltage, and temperature. The compensation may provide IO data signals with slower transition times and with reduced delays.

公开(公告)号：US20230086329A1

公开(公告)日：2023-03-23

申请号：US17931864

申请日：2022-09-13

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K3/037

Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

公开(公告)号：US20240333281A1

公开(公告)日：2024-10-03

申请号：US18598920

申请日：2024-03-07

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Sandeep KAUSHIK ,  Zia PARVEEN

IPC: H03K17/56

CPC classification number: H03K17/56

Abstract: Provided is a circuit that sets a voltage of a failsafe node. The circuit includes a first voltage setting transistor configured to operate in a conductive state to set a voltage of the failsafe node to a supply voltage of a supply voltage node. The circuit includes first and second control transistors configured to control the first voltage setting transistor to operate in the conductive state in response to both the supply voltage and a pad node voltage of a pad node corresponding to logical one and control the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero.

公开(公告)号：US20240186991A1

公开(公告)日：2024-06-06

申请号：US18443112

申请日：2024-02-15

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K3/037 ,  H03K3/13

CPC classification number: H03K3/0377 ,  H03K3/037 ,  H03K3/13

Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

公开(公告)号：US20210336606A1

公开(公告)日：2021-10-28

申请号：US17223963

申请日：2021-04-06

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

IPC: H03H11/04 ,  G06F1/10

Abstract: A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.