公开(公告)号：US20040230736A1

公开(公告)日：2004-11-18

申请号：US10760631

申请日：2004-01-20

Applicant: STMicroelectronics S.A.

Inventor： Bruno Leconte ,  Sebastien Zink ,  Paola Cavaleri

IPC: G11C005/00

CPC classification number: G11C16/08 ,  G11C8/08

Abstract: An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.

Abstract translation: 地址解码器有选择地应用于存储器阵列的字线，根据应用于解码器的字线地址而变化的可变极性，负或正的各个信号。 解码器包括传送用于选择可变极性字线组的信号的组解码器，传送用于选择可变极性字线子组的信号的至少一个子组解码器，以及字线驱动器，每个字线驱动器包括用于复用组和子组 选择信号，用于选择并选择性地将这些信号中的一个施加到字线。 优点：减少解码器的端接元件的尺寸与减少闪存中技术间距有关。

公开(公告)号：US20020119625A1

公开(公告)日：2002-08-29

申请号：US09997214

申请日：2001-11-15

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: H01L021/336

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract translation: 可由页面擦除的闪速存储器包括包含以页面排列的多个浮置栅极晶体管的闪存阵列，以及用于检查浮置栅极晶体管的阈值电压的检查电路。 具有小于给定阈值的阈值电压的编程晶体管被重新编程。 检查电路包括由至少一行浮动栅极晶体管形成的非易失性计数器，用于读取计数器中要检查的页面的地址的读取电路和用于在页面已经被加载之后递增计数器的递增电路 检查。

公开(公告)号：US20040264250A1

公开(公告)日：2004-12-30

申请号：US10789449

申请日：2004-02-26

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Zink ,  Bruno Leconte ,  Paola Cavaleri

IPC: G11C016/04

CPC classification number: G11C16/3436 ,  G11C16/04 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/50004

Abstract: An electrically erasable and programmable memory includes memory cells and a verify-program device. The memory also comprises an erase verify device arranged for supplying an erase verify signal having a determined value when a datum read in a memory cell during a first verify-program cycle has an erase logic value. Application particularly to performing a blank verify test in serial input/output Flash memories.

Abstract translation: 电可擦除和可编程存储器包括存储器单元和验证程序设备。 存储器还包括擦除验证装置，其被布置为当在第一验证程序周期期间在存储器单元中读取的数据具有擦除逻辑值时，提供具有确定值的擦除验证信号。 特别适用于在串行输入/输出闪存中执行空白验证测试。

公开(公告)号：US20030133344A1

公开(公告)日：2003-07-17

申请号：US10352581

申请日：2003-01-28

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: G11C007/00

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

公开(公告)号：US20010021958A1

公开(公告)日：2001-09-13

申请号：US09737170

申请日：2000-12-14

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Zink ,  Bruno Leconte ,  Paola Cavaleri

IPC: G06F013/00 ,  G06F012/00

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract translation: 集成电路存储器包括闪存，其包括用于记录在其输入上呈现的字的电路，而不具有并行同时记录多个字的可能性。 集成电路存储器可以包括具有足够的容量来存储多个字的缓冲存储器，其输出耦合到闪速存储器的输入端。 还包括用于将要记录到FLASH存储器中的一系列字记录到缓冲存储器中并且将首先记录到缓冲存储器中的字记录到FLASH存储器中的电路。

公开(公告)号：US20040213035A1

公开(公告)日：2004-10-28

申请号：US10775032

申请日：2004-02-09

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink

IPC: G11C011/00

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

Abstract: The present invention relates to a method for controlling and for refreshing memory cells in an electrically erasable and programmable memory comprising a memory array organized in sectors, each sector comprising memory cells linked to bit lines and to word lines. The method comprises controlling and refreshing memory cells of pages of the memory array the address of which is indicated by a control and refresh counter comprising data forming tokens usable once. According to the present invention, a control and refresh counter is integrated into each sector of the memory and comprises memory cells linked to the bit lines of the sector. A counter of a sector is erased after reaching a maximum counting value that is chosen so that, when this maximum counting value is reached, memory cells of the counter have undergone a number of electrical stress cycles that is at the most equal to a determined number. Application to Flash memories.

Abstract translation: 本发明涉及一种用于控制和刷新电可擦除可编程存储器中的存储器单元的方法，该存储器单元包括以扇区组织的存储器阵列，每个扇区包括链接到位线和字线的存储器单元。 该方法包括控制和刷新存储器阵列的存储单元，其存储单元的地址由包括可使用一次的令牌的数据形成的控制和刷新计数器指示。 根据本发明，控制和刷新计数器被集成到存储器的每个扇区中，并且包括链接到扇区的位线的存储器单元。 在达到选择的最大计数值之后擦除扇区的计数器，使得当达到该最大计数值时，计数器的存储单元已经经历了多个等于确定数量的电应力循环 。 应用于闪存。

公开(公告)号：US20020031015A1

公开(公告)日：2002-03-14

申请号：US09952904

申请日：2001-09-13

Applicant: STMicroelectronics S.A.

Inventor： Bertrand Bertrand ,  David Naura ,  Sebastien Zink

IPC: G11C005/00

CPC classification number: G11C7/12 ,  G11C16/24

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2pnull2q other data in the 2pnull2q llow-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2pnullqnull1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract translation: 集成电路存储器的列寄存器，特别是在EEPROM技术中，用于将2P位的数据字写入存储器的方法，其中p是非零整数。 该方法包括以下步骤：1）擦除字的所有单元; 2）在qp高压锁存器（HV1，HV3，HV5，HV7）中加载2q数据，并在2p-2q低压锁存器（LV0，LV2，LV4，LV6）中加载2p-2q其他数据; 和3）根据存储在2q高电压锁存器中的数据来编程存储器（M0，M2，M4，M6）的2q个单元; 以及重复2p-q-1次以下步骤：4）在步骤2）中加载2q高电压锁存器中的2q其他数据的2q高电压锁存器; 和5）根据存储在2q高电压锁存器中的数据来编程存储器（M1，M3，M5，M7）的2q个其他单元。

公开(公告)号：US20010021117A1

公开(公告)日：2001-09-13

申请号：US09795657

申请日：2001-02-28

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink

IPC: G11C019/08

CPC classification number: G11C8/00 ,  G11C7/10 ,  G11C7/103 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/30

Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.

Abstract translation: 串行输入/输出存储器能够在接收到缺少形成完整地址的N个最低有效位的部分读取地址时读取存储器中的数据。 预读步骤包括：同时读取具有相同部分地址的存储器的M个字的P个第一位; 当接收到的地址完成时，选择由完整地址指定的字的P个第一位，并将这些位传送到存储器的串行输出; 在传送P个以前的位期间读取由完整地址指定的字的P后续位，并且当P个先前的位被递送时，将这些位递送到存储器的串行输出。