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公开(公告)号：US20240128871A1
公开(公告)日：2024-04-18
申请号：US18376277
申请日：2023-10-03
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alessandro GASPARINI , Paolo MELILLO , Salvatore LEVANTINO , Massimo GHIONI
Abstract: A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.
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公开(公告)号：US20210384830A1
公开(公告)日：2021-12-09
申请号：US17335523
申请日：2021-06-01
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
Abstract: A control circuit for controlling switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse-width modulated (PWM) signal in response to a phase comparison of two clock signals. A first clock signal has a frequency determined as a function of a first feedback signal proportional to converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal, and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to a derivative of the converter output voltage. A delay line introduces a delay in the first clock signal that is dependent on the first and second currents as well as a compensation current dependent on a selected operational mode of the converter.
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公开(公告)号：US20220337198A1
公开(公告)日：2022-10-20
申请号：US17720502
申请日：2022-04-14
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Germano NICOLLINI
Abstract: An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.
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公开(公告)号：US20230336078A1
公开(公告)日：2023-10-19
申请号：US18132774
申请日：2023-04-10
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alessandro GASPARINI , Paolo MELILLO , Salvatore LEVANTINO , Massimo GHIONI
CPC classification number: H02M3/158 , H02M1/0095 , H02M3/157
Abstract: In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.
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5.发明公开公开(公告)号：US20230163767A1
公开(公告)日：2023-05-25
申请号：US17982712
申请日：2022-11-08
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
CPC classification number: H03L7/0991 , H03L7/091 , H03L7/10
Abstract: In a control circuit for a switching stage of an electronic converter, a phase detector generates a drive signal in response to a phase difference between first and second clock signals. The first and second clock signals are generated by first and second current-controlled oscillators, respectively. An operational transconductance amplifier generates first and second control currents in response to a difference between a reference and a feedback of the electronic converter, with the first and second currents applied to control the first and second current-controlled oscillators. In response to a switching clock having a first state, a switching circuit applies first and second bias currents to the control inputs of the first and second current-controlled oscillators, respectively. Conversely, in response to the switching clock having a second state, the switching circuit applies the second and first bias currents to the control inputs of the first and second current-controlled oscillators, respectively.
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Patent Agency Ranking
公开(公告)号：US20220216789A1
公开(公告)日：2022-07-07
申请号：US17569296
申请日：2022-01-05
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro GASPARINI , Alessandro BERTOLINI , Mauro LEONCINI , Massimo GHIONI , Salvatore LEVANTINO
Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.
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公开(公告)号：US20210067148A1
公开(公告)日：2021-03-04
申请号：US16559118
申请日：2019-09-03
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Stefano RAMORINI , Alessandro GASPARINI
Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.
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8.发明公开公开(公告)号：US20240356443A1
公开(公告)日：2024-10-24
申请号：US18758327
申请日：2024-06-28
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro GASPARINI , Alessandro BERTOLINI , Mauro LEONCINI , Massimo GHIONI , Salvatore LEVANTINO
CPC classification number: H02M3/158 , H02M1/0009 , H02M1/0025
Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.
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公开(公告)号：US20240348249A1
公开(公告)日：2024-10-17
申请号：US18630493
申请日：2024-04-09
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco PINZIN , Alessandro BERTOLINI , Alberto CATTANI
IPC: H03K17/687 , H02M1/088 , H02M3/157 , H02M3/158
CPC classification number: H03K17/6871 , H02M1/088 , H02M3/157 , H02M3/158
Abstract: A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.
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公开(公告)号：US20240120838A1
公开(公告)日：2024-04-11
申请号：US18376328
申请日：2023-10-03
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
CPC classification number: H02M3/158 , H02M1/0035
Abstract: In a DC-DC converter, a duty-cycle control signal is generated in response to comparing the switching stage output voltage and a reference voltage signal. A first circuit compares the duty-cycle control signal and a ramp to produce a PWM signal. A second circuit compares the duty-cycle control signal and a skip threshold to produce a skip control signal which halts switching operation of the switching stage. A count is made of number of periods of the skip control signal during a monitoring time window and the number of periods of a clock signal during a period of the skip control signal is counted. When the counted number of skip control signal periods is within a first range and the counted number of clock signal periods is within a second range, a common detection signal is asserted to trigger varying a value of the skip threshold signal.
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