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公开(公告)号：US12210089B2
公开(公告)日：2025-01-28
申请号：US18418298
申请日：2024-01-21
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Andrea Cavarra , Alessandro Finocchiaro , Giuseppe Papotto , Giuseppe Palmisano
Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·Δf, where M is an integer from 0 to N−1, where N is a number of intervals into which a frequency range for the output signal is divided, and where Δf is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.
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公开(公告)号：US09948193B2
公开(公告)日：2018-04-17
申请号：US15178822
申请日：2016-06-10
Applicant: STMicroelectronics S.r.l.
Inventor： Egidio Ragonese , Nunzio Spina , Pierpaolo Lombardo , Nunzio Greco , Alessandro Parisi , Giuseppe Palmisano
IPC: H02M3/335
CPC classification number: H02M3/33553 , H01L2224/48137 , H02M3/33523 , H02M3/33584 , H02M2001/0012
Abstract: A galvanic isolation is provided between a first circuit and a second circuit. A first galvanically isolated link is configured to transfer power from a first circuit to a second circuit across the galvanic isolation. A second galvanically isolated link is configured to feed back an error signal from the second circuit to the first circuit across the galvanic isolation for use in regulating the power transfer and further configured to support bidirectional data communication between the first and second circuits across the galvanic isolation.
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公开(公告)号：US11689156B1
公开(公告)日：2023-06-27
申请号：US17643068
申请日：2021-12-07
Applicant: STMicroelectronics S.r.l.
Inventor： Giuseppe Papotto , Alessandro Parisi , Andrea Cavarra , Giuseppe Palmisano
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1215 , H03B5/1265 , H03B2200/004
Abstract: A voltage controlled oscillator (VCO) includes: a pair of inductors coupled in series; a first pair of varactors coupled in series, and a second pair of varactors coupled in series. A first common mode node is between the respective varactors of the first pair of varactors and a second common mode node is between the respective varactors of the second pair of varactors. A supply voltage node is switchably coupled to the first common mode node through a first switch, the supply voltage node being a node located between the pair of inductors. A control voltage node (VC) is switchably coupled to the second common mode node through a second switch.
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公开(公告)号：US20230179147A1
公开(公告)日：2023-06-08
申请号：US17643068
申请日：2021-12-07
Applicant: STMicroelectronics S.r.l.
Inventor： Giuseppe Papotto , Alessandro Parisi , Andrea Cavarra , Giuseppe Palmisano
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1215 , H03B5/1265 , H03B2200/004
Abstract: A voltage controlled oscillator (VCO) includes: a pair of inductors coupled in series; a first pair of varactors coupled in series, and a second pair of varactors coupled in series. A first common mode node is between the respective varactors of the first pair of varactors and a second common mode node is between the respective varactors of the second pair of varactors. A supply voltage node is switchably coupled to the first common mode node through a first switch, the supply voltage node being a node located between the pair of inductors. A control voltage node (Vc) is switchably coupled to the second common mode node through a second switch.
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5.发明申请公开(公告)号：US20190222126A1
公开(公告)日：2019-07-18
申请号：US16244272
申请日：2019-01-10
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Nunzio Greco , Nunzio Spina , Egidio Ragonese , Giuseppe Palmisano
CPC classification number: H02M3/33523 , H01F19/08 , H01F27/2804 , H01F2019/085 , H02M1/08 , H02M3/33507 , H02M3/33515 , H02M3/33592 , H02M3/337 , H02M3/338 , H03B5/1215 , H03B5/1228 , H04L27/08
Abstract: A DC-DC converter includes a power oscillator connected to a first transformer winding, and a channel conveying a data stream through galvanic isolation by power signal modulation. A rectifier rectifies the power signal to produce a DC voltage. A comparator produces an error signal from the DC voltage and a reference voltage. An analog-to-digital converter converts the error signal to a digital power control value. A multiplexer multiplexes the digital power control value with the data stream to obtain a multiplexed bitstream. A transmitter driven by the multiplexed bitstream performs amplitude modulation of the power signal at a second transformer winding. A receiver connected to the first winding demodulates the amplitude modulated power signal. A demultiplexer demultiplexes the data stream and the digital power control value. A digital-to-analog converter converts the digital power control value to an analog control signal for the power oscillator.
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Patent Agency Ranking
公开(公告)号：US11959995B2
公开(公告)日：2024-04-16
申请号：US17395080
申请日：2021-08-05
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Finocchiaro , Alessandro Parisi , Andrea Cavarra , Giuseppe Papotto , Giuseppe Palmisano
IPC: G01S13/34 , G01S13/931 , H03B5/12 , H03L7/193 , G01S13/00
CPC classification number: G01S13/34 , G01S13/931 , H03B5/1231 , H03L7/193
Abstract: A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.
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公开(公告)号：US11879963B2
公开(公告)日：2024-01-23
申请号：US18108993
申请日：2023-02-13
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Andrea Cavarra , Alessandro Finocchiaro , Giuseppe Papotto , Giuseppe Palmisano
CPC classification number: G01S13/584 , G01S7/4056 , G01S13/931 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03L7/099 , H03L7/101 , H03L7/103 , H03L7/193
Abstract: Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.
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公开(公告)号：US10917091B2
公开(公告)日：2021-02-09
申请号：US16371919
申请日：2019-04-01
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Nunzio Greco , Nunzio Spina , Egidio Ragonese , Giuseppe Palmisano
IPC: H03K7/08 , H03K17/691 , H03K17/723 , H03K17/722 , H03B5/06 , H03L7/08 , H03L7/06 , H03L7/183 , H02M3/335 , H02M1/00 , H01F19/08
Abstract: An oscillator is coupled to a first side of a galvanic barrier for supplying thereto an electric supply signal. The oscillator is configured to be alternatively turned on and off as a function of a PWM drive signal applied thereto. A receiver circuit coupled to the galvanic barrier receives therefrom a PWM power control signal. A signal reconstruction circuit coupled between the receiver circuit block and the oscillator provides to the oscillator a PWM drive signal reconstructed from the PWM power control signal. The signal reconstruction circuit includes a PLL circuit coupled to the receiver circuit block and configured to lock to the PWM control signal from the receiver circuit block. A PLL loop within the PLL circuit is sensitive to the PWM drive signal applied to the oscillator. The PLL loop is configured to be opened as a result of the power supply oscillator being turned off.
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公开(公告)号：US10193581B2
公开(公告)日：2019-01-29
申请号：US15468306
申请日：2017-03-24
Applicant: STMicroelectronics S.r.l.
Inventor： Egidio Ragonese , Nunzio Spina , Alessandro Parisi , Pierpaolo Lombardo , Nunzio Greco , Giuseppe Palmisano
Abstract: A galvanic isolation circuit is formed by a differential transformer having primary and secondary windings for transmission of signals over a carrier between the primary and the secondary windings of the transformer. A galvanic isolation oxide layer is provide between the primary and secondary windings. Each winding includes include a center tap providing a low-impedance paths for dc and low frequency components of common-mode currents through the differential transformer. A pass-band stage is coupled to the secondary winding of the transformer and configured to permit propagation of signals over said carrier through the pass-band amplifier stage while providing for a rejection of common-mode noise.
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公开(公告)号：US11611280B2
公开(公告)日：2023-03-21
申请号：US17404382
申请日：2021-08-17
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Nunzio Greco , Nunzio Spina , Egidio Ragonese , Giuseppe Palmisano
IPC: H02M3/335 , H02M1/08 , H04L27/08 , H01F19/08 , H01F27/28 , H03B5/12 , H02M3/338 , H02M3/337 , H02M3/00
Abstract: A DC-DC converter includes: an transformer having a primary winding and a secondary winding magnetically coupled to the primary winding; a power oscillator applying an oscillating signal to the primary to transmit a power signal to the secondary winding; a rectifier connected to the secondary winding of the transformer to obtain an output DC voltage by rectification of the power signal; comparison circuitry to generate an error signal representing a difference between the output DC voltage and a reference voltage; a transmitter connected to the secondary winding of the transformer to apply an amplitude modulation to the power signal at the secondary winding of the transformer in response to the error signal to thereby produce an amplitude modulated signal at the primary winding; and a receiver and control circuit connected to the primary winding to control an amplitude of the oscillating signal as a function of the amplitude modulated signal.
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