HIGH SPEED DATA TRANSMISSION IN BATTERY MANAGEMENT SYSTEMS WITH ISOLATED SPI INTERFACE

    公开(公告)号:US20240345987A1

    公开(公告)日:2024-10-17

    申请号:US18756821

    申请日:2024-06-27

    CPC classification number: G06F13/4291 G06F13/364 G06F13/4022

    Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

    High speed data transmission in battery management systems with isolated SPI interface

    公开(公告)号:US12056080B2

    公开(公告)日:2024-08-06

    申请号:US17732114

    申请日:2022-04-28

    CPC classification number: G06F13/4291 G06F13/364 G06F13/4022

    Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

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