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    Memory device including reference bit line for increasing read operation accuracy
    5.
    发明授权
    Memory device including reference bit line for increasing read operation accuracy 有权

    公开(公告)号：US12200927B2

    公开(公告)日：2025-01-14

    申请号：US17576544

    申请日：2022-01-14

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Yosuke Nosho ,  Takashi Ohashi ,  Shohei Kamisaka ,  Takashi Hirotani

    IPC: H10B43/23 ,  G11C7/06 ,  G11C7/14 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/23 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

    Abstract: A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.

    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20220238536A1

    公开(公告)日：2022-07-28

    申请号：US17576544

    申请日：2022-01-14

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Yosuke Nosho ,  Takashi Ohashi ,  Shohei Kamisaka ,  Takashi Hirotani

    IPC: H01L27/1158 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11565 ,  G11C7/18 ,  G11C8/14

    Abstract: A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.

    THREE-DIMENSIONAL MEMORY STRUCTURE FABRICATED USING REPEATED ACTIVE STACK SECTIONS
    7.
    发明申请
    THREE-DIMENSIONAL MEMORY STRUCTURE FABRICATED USING REPEATED ACTIVE STACK SECTIONS 有权

    公开(公告)号：US20220383953A1

    公开(公告)日：2022-12-01

    申请号：US17730056

    申请日：2022-04-26

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Shohei Kamisaka ,  Vinod Purayath ,  Jie Zhou

    IPC: G11C16/04 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/786 ,  H01L29/66

    Abstract: A method for forming a three-dimensional memory structure above a semiconductor substrate includes forming two or more active stack sections, each formed on top of each other and separated by a dielectric buffer layer, where each active stack section includes multilayers separated by isolation dielectric layers and trenches with shafts filled with a sacrificial material. After the multiple active stack sections are formed, the method removes the sacrificial material in the shafts and removes portions of the dielectric buffer layer between shafts of adjacent active stack sections. The method fills the openings with a gate dielectric layer and a gate conductor. In some embodiments, the gate dielectric layer is discontinuous in the shaft over the depth of the multiple active stack sections.

    BIT LINE AND SOURCE LINE CONNECTIONS FOR A 3-DIMENSIONAL ARRAY OF MEMORY CIRCUITS
    9.
    发明申请
    BIT LINE AND SOURCE LINE CONNECTIONS FOR A 3-DIMENSIONAL ARRAY OF MEMORY CIRCUITS 有权

    公开(公告)号：US20220199532A1

    公开(公告)日：2022-06-23

    申请号：US17548034

    申请日：2021-12-10

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Shohei Kamisaka ,  Yosuke Nosho

    IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

    Abstract: A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via.

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