公开(公告)号：US12200927B2

公开(公告)日：2025-01-14

申请号：US17576544

申请日：2022-01-14

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Yosuke Nosho ,  Takashi Ohashi ,  Shohei Kamisaka ,  Takashi Hirotani

IPC: H10B43/23 ,  G11C7/06 ,  G11C7/14 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/23 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.

公开(公告)号：US20220238536A1

公开(公告)日：2022-07-28

申请号：US17576544

申请日：2022-01-14

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Yosuke Nosho ,  Takashi Ohashi ,  Shohei Kamisaka ,  Takashi Hirotani

IPC: H01L27/1158 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11565 ,  G11C7/18 ,  G11C8/14

Abstract: A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.

公开(公告)号：US20240347109A1

公开(公告)日：2024-10-17

申请号：US18629205

申请日：2024-04-08

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Masahiro Yoshihara ,  Takashi Hirotani

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/08 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/08 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20

Abstract: A memory circuit includes an array of thin-film ferroelectric memory transistors formed by an array of NOR memory strings intersecting with local word line structures with global word lines arranged orthogonal to the array of NOR memory strings and aligned with a set of local word line structures provided across multiple stacks of NOR memory strings. The memory circuit includes a word line select transistor associated with each local word line structure to isolate each local word line structure from the associated global word line. The word line select transistor, when activated, selectively couples a selected local word line structure to the associated global word line. Remaining local word line structures associated with the same global word line remain disconnected and therefore not selected. In this manner, parasitic capacitance on the global word line is reduced and unintended disturb to other unselected memory transistors is also reduced.

公开(公告)号：US20230371266A1

公开(公告)日：2023-11-16

申请号：US18156959

申请日：2023-01-19

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Minori Kajimoto ,  Takashi Hirotani ,  Masahiro Yoshihara

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/30 ,  H01L23/528 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B51/20 ,  H01L23/5283 ,  H01L29/66742 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7869 ,  H10B51/10 ,  H10B51/30

Abstract: A memory device includes a stacked body of alternately arranged conductor-including layers and insulating films in the first direction and pillar bodies within the stacked body. Each pillar body includes first and second conductive pillars and an insulator pillar located between the first conductive pillar and the second conductive pillar. Each conductor-including layer includes a semiconductor member, an electrode film and a ferroelectric layer provided between the semiconductor member and the electrode film. The semiconductor members in the multiple conductor-including layers are separated from each other in the first direction.