公开(公告)号：US20190139613A1

公开(公告)日：2019-05-09

申请号：US16048786

申请日：2018-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-yeon SHIN ,  Jeong-don IHM ,  Byung-hoon JEONG ,  Jung-june PARK

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/32

Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

公开(公告)号：US20230205711A1

公开(公告)日：2023-06-29

申请号：US18170949

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-joo JUNG ,  Jang-Woo LEE ,  Byung-hoon JEONG ,  Jeong-don IHM

IPC: G06F13/16 ,  G06F11/30 ,  G06F11/07 ,  G06F1/10 ,  G06F12/0882 ,  G06F18/214

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F11/0757 ,  G06F11/3037 ,  G06F12/0882 ,  G06F18/2148

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

公开(公告)号：US20210391023A1

公开(公告)日：2021-12-16

申请号：US17460954

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-yeon SHIN ,  Jeong-don IHM ,  Byung-hoon JEONG ,  Jung-june PARK

IPC: G11C16/30 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  G11C7/10 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/1157

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

公开(公告)号：US20170052225A1

公开(公告)日：2017-02-23

申请号：US15170940

申请日：2016-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-kyoo LEE ,  Jeong-don IHM ,  Byung-hoon JEONG ,  Dae-woon KANG ,  Tae-sung LEE ,  Sang-lok KIM

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/318392 ,  G01R31/31708

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract translation: 半导体芯片，测试系统和测试半导体芯片的方法。 半导体芯片包括：脉冲发生器，被配置为响应于测试请求产生测试脉冲; 逻辑链，包括彼此串联连接并顺次传送测试脉冲的多个逻辑器件; 以及检测器，被配置为检测每个逻辑器件的输出信号的逻辑电平，并输出指示符号间干扰程度（ISI）的检测结果。

公开(公告)号：US20190158109A1

公开(公告)日：2019-05-23

申请号：US16191367

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil KAVALA ,  Seon-kyoo LEE ,  Byung-hoon JEONG ,  Jeong-don IHM ,  Young-don CHOI

IPC: H03M1/78 ,  G11C5/14 ,  G05F3/08

CPC classification number: H03M1/785 ,  G05F3/08 ,  G11C5/147 ,  G11C7/14

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

公开(公告)号：US20190096447A1

公开(公告)日：2019-03-28

申请号：US15975266

申请日：2018-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-SU JANG ,  Man-jae YANG ,  Jeong-don IHM ,  Go-eun JUNG ,  Byung-hoon JEONG ,  Young-don CHOI

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C7/106 ,  G11C5/066 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C16/26 ,  G11C2207/107

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US20190079699A1

公开(公告)日：2019-03-14

申请号：US15979625

申请日：2018-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-woo LEE ,  Jeong-don IHM ,  Byung-hoon JEONG

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/22 ,  G11C29/023 ,  G11C29/028

Abstract: A memory system and a buffer device include a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices and a buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signal delay circuit, and the memory controller performs the training operations by controlling the training block.