SEMICONDUCTOR DEVICE
    1.
    发明公开

    公开(公告)号:US20240322012A1

    公开(公告)日:2024-09-26

    申请号:US18602274

    申请日:2024-03-12

    Abstract: A semiconductor device including an active region extending in a first horizontal direction, a nanosheet stack apart from the active region, a plurality of gate structures extending in a second horizontal direction and including a plurality of gate electrodes, a plurality of source/drain regions arranged on sidewalls of the gate structures, and a device isolation layer extending in a vertical direction, wherein the plurality of gate structures include a first gate structure in which a source/drain region is arranged on one sidewall and the device isolation layer is arranged on the other sidewall, and a second gate structure in which source/drain regions are arranged on both sidewalls, wherein the plurality of gate electrodes of the first gate structure include a main gate electrode positioned at the uppermost end and a plurality of sub-gate electrodes, and an internal spacer is between the device isolation layer and the plurality of sub-gate electrodes.

    SEMICONDUCTOR DEVICE
    3.
    发明申请

    公开(公告)号:US20240405073A1

    公开(公告)日:2024-12-05

    申请号:US18538290

    申请日:2023-12-13

    Abstract: A semiconductor device is provided including an active pattern disposed on a substrate, a source/drain pattern on the active pattern, a channel pattern configured to electrically connect the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, a gate pattern configured to cross between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and to have a main gate portion and sub-gate portions, and inner gate spacers between the sub-gate portions and the source/drain pattern. A first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between adjacent source/drain patterns passing through the semiconductor patterns in the second direction.

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