公开(公告)号：US20240038763A1

公开(公告)日：2024-02-01

申请号：US18486331

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L2027/11829 ,  H01L2027/11851 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20230231026A1

公开(公告)日：2023-07-20

申请号：US17890547

申请日：2022-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungkyu KIM ,  Yonghee PARK ,  Dong-Gwan SHIN ,  Dae Sin KIM ,  Sangyong KIM ,  Joohyung YOU

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L29/6656 ,  H01L29/78696 ,  H01L29/0847

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.

公开(公告)号：US20220157853A1

公开(公告)日：2022-05-19

申请号：US17369236

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.