公开(公告)号：US20220157853A1

公开(公告)日：2022-05-19

申请号：US17369236

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20250056897A1

公开(公告)日：2025-02-13

申请号：US18794027

申请日：2024-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Duckseoung KANG ,  Sangdeok KWON ,  Gibum KIM ,  Seungjae LEE

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/78 ,  H01L29/861

Abstract: An integrated circuit device includes: a substrate including a first surface and a second surface that is opposite to the first surface; and a diode structure including: an upper semiconductor layer disposed on the first surface of the substrate and including a first dopant of a first conductivity type; a lower semiconductor layer disposed on the second surface of the substrate and including a second dopant of a second conductivity type that is different from the first conductivity type; and a first well region provided in a portion of the substrate that is between the upper semiconductor layer and the lower semiconductor layer, wherein the first well region is in contact with the upper semiconductor layer or the lower semiconductor layer.

公开(公告)号：US20240387624A1

公开(公告)日：2024-11-21

申请号：US18532576

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Duckseoung KANG ,  Sangdeok KWON ,  Gibum KIM

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a substrate including a first surface and a second surface that are opposite to each other, a fin type active area extending from the first surface of the substrate in a first direction, a channel structure on an upper surface of the fin type active area and including a channel region, a source/drain region on the upper surface of the fin type active area, a gate line extending on the substrate in a second direction that is perpendicular to the first direction, disposed on the substrate, and surrounding the channel structure, and an isolation structure passing vertically through the substrate and the fin type active area and located at one side of the source/drain region, wherein the channel structure, the source/drain region, and the isolation structure are sequentially arranged in the first direction.

公开(公告)号：US20250142905A1

公开(公告)日：2025-05-01

申请号：US18653475

申请日：2024-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Duckseoung KANG ,  Sangdeok KWON ,  Gibum KIM

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include first, second, and third source/drain patterns, semiconductor patterns between the first and third source/drain patterns, a gate dielectric layer in contact with the semiconductor patterns, a gate electrode in contact with the gate dielectric layer, blocking semiconductor patterns between the first and second source/drain patterns, a blocking dielectric layer in contact with the blocking semiconductor patterns, and a blocking electrode in contact with the blocking dielectric layer. The blocking dielectric layer may include a first layer in contact with the first and second source/drain patterns, a second layer in contact with the blocking electrode, and a third layer between the first and second layers. A dielectric material of the third layer may be different than a dielectric material of the first layer and that of the second layer.

公开(公告)号：US20240038763A1

公开(公告)日：2024-02-01

申请号：US18486331

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L2027/11829 ,  H01L2027/11851 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20240363493A1

公开(公告)日：2024-10-31

申请号：US18524812

申请日：2023-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Duckseoung KANG ,  Sangdeok KWON ,  Gibum KIM

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a semiconductor substrate, a channel pattern on a first surface of the semiconductor substrate, source/drain patterns on the first surface of the semiconductor substrate and on both sides of the channel pattern, a contact electrode electrically connected to the source/drain patterns, a lower wiring structure on the second surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and connecting the contact electrode and the lower wiring structure to each other. The lower wiring structure may include a first metal line connected to a first voltage, a second metal line connected to a second voltage, and an auxiliary electrode electrically connected to one of the first metal line and the second metal line. The auxiliary electrode may overlap and be insulated from an other of the first metal line and the second metal line.

公开(公告)号：US20220328496A1

公开(公告)日：2022-10-13

申请号：US17541790

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Seunghun LEE ,  Sangdeok KWON ,  Keun Hwi CHO ,  Sung Gi HUR

IPC: H01L27/11 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the pair of first source/drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cutting pattern that is adjacent to the first channel pattern and penetrates the first gate electrode, and a first residual pattern between the first gate cutting pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes, on an upper portion of the first gate electrode, a first extension that vertically overlaps the first residual pattern.