公开(公告)号：US20230328989A1

公开(公告)日：2023-10-12

申请号：US18209983

申请日：2023-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Yong CHUNG ,  Ho Jin KIM ,  Young-Jin KWON ,  Dong Seog EUN

IPC: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

公开(公告)号：US20210028190A1

公开(公告)日：2021-01-28

申请号：US17028047

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won KIM ,  Kwang Young JUNG ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US20210335811A1

公开(公告)日：2021-10-28

申请号：US17143216

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Yong CHUNG ,  Ho Jin KIM ,  Young-Jin KWON ,  Dong Seog EUN

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  G11C8/14

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

公开(公告)号：US20200135761A1

公开(公告)日：2020-04-30

申请号：US16719089

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won KIM ,  Kwang Young JUNG ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C16/10 ,  G11C7/14 ,  H01L27/11526 ,  G11C11/4099 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US20180350831A1

公开(公告)日：2018-12-06

申请号：US15841523

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C11/4099 ,  G11C16/10 ,  G11C7/14 ,  H01L27/11526

CPC classification number: H01L27/11582 ,  G11C7/14 ,  G11C11/4099 ,  G11C16/107 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.