公开(公告)号：US11296110B2

公开(公告)日：2022-04-05

申请号：US16797884

申请日：2020-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang Young Jung ,  Jong Won Kim ,  Young Hwan Son ,  Jee Hoon Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/423

Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.

公开(公告)号：US10854631B2

公开(公告)日：2020-12-01

申请号：US16719089

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US10950620B2

公开(公告)日：2021-03-16

申请号：US16242410

申请日：2019-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Young Jung ,  Dong Won Kim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/423

Abstract: A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.

公开(公告)号：US10546874B2

公开(公告)日：2020-01-28

申请号：US15841523

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: G11C8/00 ,  H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US11974433B2

公开(公告)日：2024-04-30

申请号：US17575947

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US20180350831A1

公开(公告)日：2018-12-06

申请号：US15841523

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C11/4099 ,  G11C16/10 ,  G11C7/14 ,  H01L27/11526

CPC classification number: H01L27/11582 ,  G11C7/14 ,  G11C11/4099 ,  G11C16/107 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US11227870B2

公开(公告)日：2022-01-18

申请号：US16739392

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US10964720B2

公开(公告)日：2021-03-30

申请号：US17028047

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  H01L27/11565 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  G11C7/14

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.