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公开(公告)号：US20190148456A1
公开(公告)日：2019-05-16
申请号：US16226855
申请日：2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
CPC classification number: H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.
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Patent Agency Ranking
公开(公告)号：US20180026077A1
公开(公告)日：2018-01-25
申请号：US15421498
申请日：2017-02-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
CPC classification number: H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U (1) (where 0.05≦X≦0.1, 0.15≦Y≦0.25, 0.7≦Z≦0.8, X+Y+Z=1, 0.45≦a≦0.6, and 0.08≦U≦0.2).
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公开(公告)号：US10224371B2
公开(公告)日：2019-03-05
申请号：US15421498
申请日：2017-02-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
Abstract: A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U (1) (where 0.05≤X≤0.1, 0.15≤Y≤0.25, 0.7≤Z≤0.8, X+Y+Z=1, 0.45≤a≤0.6, and 0.08≤U≤0.2).
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公开(公告)号：US10186552B2
公开(公告)日：2019-01-22
申请号：US15446024
申请日：2017-03-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seol Choi , Hideki Horii , Dong-ho Ahn , Seong-geon Park , Dong-jun Seong , Min-kyu Yang , Jung-moo Lee
Abstract: A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.
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公开(公告)号：US10546894B2
公开(公告)日：2020-01-28
申请号：US16226855
申请日：2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.
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公开(公告)号：US20180033826A1
公开(公告)日：2018-02-01
申请号：US15446024
申请日：2017-03-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seol Choi , Hideki Horii , Dong-ho Ahn , Seong-geon Park , Dong-jun Seong , Min-kyu Yang , Jung-moo Lee
CPC classification number: H01L27/2427 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C2213/52 , G11C2213/71 , G11C2213/72 , G11C2213/73 , G11C2213/76 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.
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