公开(公告)号：US20230284450A1

公开(公告)日：2023-09-07

申请号：US18097332

申请日：2023-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsik LEE ,  HYUK KIM ,  YEONGEUN YOOK

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A semiconductor device and an electronic system including the same are provided. The semiconductor device may include a stacked structure including electrodes stacked on a substrate, interlayer insulating layers interposed between the electrodes, and an upper insulating layer covering the uppermost electrode among the electrodes, and a vertical structure passing through the stacked structure in a vertical direction, and each of the interlayer insulating layers may have a first thickness, and the upper insulating layer may have a second thickness greater than the first thickness, and the upper insulating layer may include an insulating material different from an insulating material of each of the interlayer insulating layers.

公开(公告)号：US20230147901A1

公开(公告)日：2023-05-11

申请号：US17819330

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIN YOUNG PARK ,  HYUK KIM ,  YEON GEUN YOOK ,  YOUNG SIK LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573

Abstract: Semiconductor memory devices may include a cell substrate including a cell array region, first and second extension regions and a through region, a first mold structure including first gate electrodes stacked in a stepwise manner, a first interlayer insulating layer extending conformally on the first gate electrodes on the second extension region, a second interlayer insulating layer on the first interlayer insulating layer, a second mold structure including second gate electrodes on the second interlayer insulating layer and stacked on the first extension region in the stepwise manner, a channel structure in the first and second mold structures on the cell array region, a first cell contact structure in the first mold structure on the second extension region, and a second cell contact structure in the first and second mold structures on the first extension region. The first and second interlayer insulating layers may have different impurity concentrations.

公开(公告)号：US20190122903A1

公开(公告)日：2019-04-25

申请号：US15972350

申请日：2018-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG BO SHIM ,  HYUK KIM ,  SUN TAEK LIM ,  JAE MYUNG CHOE ,  JEON IL LEE ,  SUNG-IL CHO

IPC: H01L21/67 ,  H01L21/683 ,  H01J37/32 ,  H01L21/3065

Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.