公开(公告)号：US20170287787A1

公开(公告)日：2017-10-05

申请号：US15624039

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young KIM ,  JinTae KIM ,  Jae-Woo SEO ,  Dong-yeon HEO

IPC: H01L21/8234 ,  G06F17/50 ,  H01L21/768 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L21/823475 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76892 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：US20170133367A1

公开(公告)日：2017-05-11

申请号：US15416016

申请日：2017-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-Young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

公开(公告)号：US20200212069A1

公开(公告)日：2020-07-02

申请号：US16817094

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/66 ,  H01L21/8238 ,  H01L49/02 ,  H01L27/11582 ,  G03F1/36 ,  G06F30/398 ,  G06F30/394 ,  G06F30/327 ,  G06F30/30

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20170062403A1

公开(公告)日：2017-03-02

申请号：US15238912

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/02 ,  G03F1/36 ,  H01L21/8238 ,  G06F17/50 ,  H01L21/66 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract translation: 半导体器件包括包括第一有源区和第二有源区的衬底，第一有源区具有不同于第二有源区的导电类型的导电类型，并且第一有源区与第二有源区间隔开 区域，第一方向上延伸的栅电极，与第一有源区和第二有源区交叉的栅电极，设置在第一有源区的上部的第一浅隔离图案，第一浅隔离图案延伸 以及设置在第二有源区的上部的深隔离图案，深隔离图案沿第一方向延伸，深隔离图案将第二有源区分割成第一区域和第二区域。

公开(公告)号：US20180019736A1

公开(公告)日：2018-01-18

申请号：US15649776

申请日：2017-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young KIM ,  DALHEE LEE ,  Hyoung-Suk OH ,  Keunho LEE ,  TAEJOONG SONG ,  SUNGWE CHO

IPC: H03K3/356 ,  H03K23/00

CPC classification number: H03K3/356104 ,  H03K3/35625 ,  H03K23/001

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

公开(公告)号：US20140225889A1

公开(公告)日：2014-08-14

申请号：US14176301

申请日：2014-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young KIM ,  Hyoung-Min PARK ,  Haesun PARK ,  Jae-Gul CHOO

IPC: G06T15/00

CPC classification number: G06T11/206 ,  G06T19/00

Abstract: A method and an apparatus are provided to visualize high-dimensional data. The method includes primarily visualizing the high-dimensional data at a dimension lower than the high-dimensional data to obtain a primarily-visualized image. The method also includes secondarily visualizing the high-dimensional data in an area of the primarily-visualized image at a dimension higher than the primarily-visualized image to obtain a secondarily-visualized image.

Abstract translation: 提供了一种可视化高维数据的方法和装置。 该方法主要包括在低于高维数据的维度上可视化高维数据以获得主要可视化图像。 该方法还包括以高于主要可视化图像的维度将主要可视化图像的区域中的高维数据二次可视化以获得二次可视化图像。

公开(公告)号：US20140200452A1

公开(公告)日：2014-07-17

申请号：US14155721

申请日：2014-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chu-Ho CHANG ,  Yeong-Kyeong SEONG ,  Ha-Young KIM ,  Kyoung-Gu WOO

IPC: G06T7/00 ,  G06F3/0484 ,  A61B8/08 ,  G06F3/0482

CPC classification number: G06F3/04842 ,  A61B8/0825 ,  A61B8/469 ,  A61B8/5215 ,  A61B8/5223 ,  G06T7/12 ,  G06T2207/10132 ,  G06T2207/20104 ,  G06T2207/20161 ,  G06T2207/30068

Abstract: There is provided an image segmentation apparatus and related method for enhancing accuracy of image segmentation based on user interaction. The image segmentation apparatus including an interface configured to, in response to an image displayed on the interface, receive information about the image from a user and a segmenter configured to segment the contour of a region of interest (ROI) in the image based on the information.

Abstract translation: 提供了一种基于用户交互提高图像分割精度的图像分割装置及相关方法。 该图像分割装置包括被配置为响应于在界面上显示的图像接收来自用户的图像的信息的接口和被配置为基于图像划分图像中的感兴趣区域（ROI）的轮廓的分割器 信息。

公开(公告)号：US20210210479A1

公开(公告)日：2021-07-08

申请号：US17009941

申请日：2020-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon KANG ,  Subin JIN ,  Ha-Young KIM

IPC: H01L27/02 ,  H03K3/037 ,  H03K3/3562

Abstract: A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

公开(公告)号：US20180350838A1

公开(公告)日：2018-12-06

申请号：US16043236

申请日：2018-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  H01L21/66 ,  G06F17/50 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/092 ,  H01L27/02 ,  G03F1/36 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20170062475A1

公开(公告)日：2017-03-02

申请号：US15282206

申请日：2016-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  G03F1/36 ,  G06F17/50

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.