公开(公告)号：US20210057538A1

公开(公告)日：2021-02-25

申请号：US16841889

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Hyunjoon ROH ,  Heungsik PARK ,  Sughyun SUNG ,  Dohaing LEE ,  Wonhyuk LEE

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US20160233310A1

公开(公告)日：2016-08-11

申请号：US14970710

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young Lee ,  Dohyoung KIM ,  Johnsoo KIM ,  Heungsik PARK ,  Hongsik SHIN ,  Younghun CHOI

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Abstract translation: 形成半导体器件的方法包括在衬底上形成栅电极，在栅电极的侧壁上形成第一间隔物，在第一间隔物上形成第二间隔物，并在栅电极的顶表面上形成封盖图案， 第一间隔物和第二间隔物。 第二间隔件的外侧壁与封盖图案的侧壁垂直对齐。

公开(公告)号：US20240347424A1

公开(公告)日：2024-10-17

申请号：US18531235

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik SHIN ,  Kyongbeom KOH ,  Eunkyung KO ,  Hyonwook RA ,  Dongsoo SEO ,  Jeongyeon SEO ,  Kwangyong YANG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device may include an active region extending in a first direction; a gate structure extending in a second direction on the active region; a source/drain region on the active region and disposed at least one side of the gate structure; a contact structure on the source/drain region; a device isolation layer surrounding the active region; an interlayer insulating layer on the device isolation layer, the gate structure, and the source/drain region; a vertical power structure penetrating through the device isolation and interlayer insulating layers and connected to the contact structure; a rear power structure electrically connected to the vertical power structure and surrounding an entirety of a lower surface and a portion of a side surface of the vertical power structure; a vertical insulating film between the vertical power structure and the rear power structure; and a rear insulating film covering a side of the rear power structure.

公开(公告)号：US20210296254A1

公开(公告)日：2021-09-23

申请号：US17338787

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Sanghyun LEE ,  Hakyoon AHN ,  Seonghan OH ,  Youngmook OH

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088 ,  H01L49/02 ,  H01L21/8234 ,  H01L27/06

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

公开(公告)号：US20220376080A1

公开(公告)日：2022-11-24

申请号：US17837158

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Hyunjoon ROH ,  Heungsik PARK ,  Sughyun SUNG ,  Dohaing LEE ,  Wonhyuk LEE

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US20220189870A1

公开(公告)日：2022-06-16

申请号：US17373900

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Dong Kwon KIM ,  Jinwook LEE ,  Jongchul PARK ,  Wonhyuk LEE

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.