公开(公告)号：US12293807B2

公开(公告)日：2025-05-06

申请号：US18347641

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younggil Go ,  Hundae Choi ,  Yoochang Sung

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/22

Abstract: An offset calibration training method for adjusting a data receiver offset and a memory device therefor are provided. A method of performing a data receiver offset calibration includes storing a first parameter code, which is used to set a default data receiver offset calibration for the data receiver offset calibration, in a mode register, storing a second parameter code, which is used to set an optional data receiver offset calibration for the data receiver offset calibration, in the mode register, training the default data receiver offset calibration based on the first parameter code for the data receiver offset calibration, and training the optional data receiver offset calibration based on the second parameter code for the data receiver offset calibration.

公开(公告)号：US11705172B2

公开(公告)日：2023-07-18

申请号：US17567306

申请日：2022-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Chang ,  Hundae Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C29/023

Abstract: A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.

公开(公告)号：US11456046B2

公开(公告)日：2022-09-27

申请号：US17225548

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hundae Choi

IPC: G11C29/12 ,  G11C29/46 ,  G11C29/36 ,  H03L7/083 ,  H03L7/08 ,  H03L7/081

Abstract: A clock locking method of a memory device, may include performing an initial locking operation in a delay locked loop circuit before an internal voltage is stabilized, monitoring clock skew between a reference clock and a feedback clock using a window detection circuit after the internal voltage is stabilized, and performing a re-locking operation in the delay locked loop circuit using a dynamic delay control corresponding to the clock skew.

公开(公告)号：US11437085B2

公开(公告)日：2022-09-06

申请号：US17139538

申请日：2020-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae Choi ,  Garam Choi

IPC: G11C11/4076 ,  H03L7/081 ,  H03L7/085

Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

公开(公告)号：US20240029768A1

公开(公告)日：2024-01-25

申请号：US18347641

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younggil Go ,  Hundae Choi ,  Yoochang Sung

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/08

CPC classification number: G11C7/1093 ,  G11C7/222 ,  G11C7/08 ,  G11C7/1084

Abstract: An offset calibration training method for adjusting a data receiver offset and a memory device therefor are provided. A method of performing a data receiver offset calibration includes storing a first parameter code, which is used to set a default data receiver offset calibration for the data receiver offset calibration, in a mode register, storing a second parameter code, which is used to set an optional data receiver offset calibration for the data receiver offset calibration, in the mode register, training the default data receiver offset calibration based on the first parameter code for the data receiver offset calibration, and training the optional data receiver offset calibration based on the second parameter code for the data receiver offset calibration.

公开(公告)号：US11869574B2

公开(公告)日：2024-01-09

申请号：US17674908

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Chang ,  Hundae Choi

IPC: G11C11/4076 ,  G11C11/4093 ,  H03K3/017 ,  H01L25/18 ,  H01L25/065

CPC classification number: G11C11/4076 ,  G11C11/4093 ,  H03K3/017 ,  H01L25/0657 ,  H01L25/18

Abstract: A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.

公开(公告)号：US11799463B2

公开(公告)日：2023-10-24

申请号：US17842881

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae Choi ,  Garam Choi

IPC: H03K5/156 ,  H03L7/081 ,  G11C8/18 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: H03K5/1565 ,  G11C7/222 ,  G11C8/10 ,  G11C8/18 ,  H03L7/0812 ,  G11C7/1057 ,  G11C7/1084

Abstract: A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.

公开(公告)号：US20230029968A1

公开(公告)日：2023-02-02

申请号：US17674908

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Chang ,  Hundae Choi

IPC: G11C11/4076 ,  G11C11/4093 ,  H03K3/017

Abstract: A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.

公开(公告)号：US11568916B2

公开(公告)日：2023-01-31

申请号：US17811503

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae Choi ,  Garam Choi

IPC: G11C11/4076 ,  H03L7/081 ,  H03L7/085

Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

公开(公告)号：US11329654B2

公开(公告)日：2022-05-10

申请号：US17149039

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae Choi ,  Garam Choi

IPC: H03L7/081 ,  G11C11/4076

Abstract: A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.