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公开(公告)号：US11715525B2
公开(公告)日：2023-08-01
申请号：US17408921
申请日：2021-08-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jun-Ho Seo , Yong-Lae Kim , Haneol Jang , Hyukje Kwon , Sang-Wan Nam
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/10 , H10B43/27
Abstract: A nonvolatile memory device includes a memory block including a first structure formed on a substrate and a second structure formed on the first structure. An erase method of the nonvolatile memory device includes applying a word line erase voltage to first normal word lines of the first structure and second normal word lines of the second structure, and applying a junction word line erase voltage smaller than the word line erase voltage to at least one of a first junction word line of the first structure and a second junction word line of the second structure. The first junction word line is a word line adjacent to the second structure from among word lines of the first structure, and the second junction word line is a word line adjacent to the first structure from among word lines of the second structure.
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2.发明申请公开(公告)号：US20210265000A1
公开(公告)日：2021-08-26
申请号：US17018418
申请日：2020-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungsuk Yu , Hyukje Kwon , Jisoo Choi
Abstract: A method of testing a semiconductor package including a plurality of semiconductor chips includes sensing electrical signals respectively output from a plurality of semiconductor chip groups each representing a combination of at least two semiconductor chips among the plurality of semiconductor chips, obtaining amplitudes of electrical signals respectively output from the plurality of semiconductor chips based on the plurality of sensed electrical signals, and outputting a test result for the semiconductor package by using the plurality of obtained electrical signals.
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3.发明授权公开(公告)号：US11568949B2
公开(公告)日：2023-01-31
申请号：US17018418
申请日：2020-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungsuk Yu , Hyukje Kwon , Jisoo Choi
Abstract: A method of testing a semiconductor package including a plurality of semiconductor chips includes sensing electrical signals respectively output from a plurality of semiconductor chip groups each representing a combination of at least two semiconductor chips among the plurality of semiconductor chips, obtaining amplitudes of electrical signals respectively output from the plurality of semiconductor chips based on the plurality of sensed electrical signals, and outputting a test result for the semiconductor package by using the plurality of obtained electrical signals.
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公开(公告)号：US20220130849A1
公开(公告)日：2022-04-28
申请号：US17350760
申请日：2021-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyukje Kwon , Byungyong Choi , Jisang Lee
IPC: H01L27/11573 , H01L27/11556 , H01L27/11529 , H01L27/11582 , G11C16/04 , G11C16/08 , G11C16/24
Abstract: A memory device includes a cell region in which memory blocks, respectively including gate electrodes and insulating layers, alternately stacked on a substrate, and channel structures, extending in a first direction, perpendicular to an upper surface of the substrate, passing through the gate electrodes and the insulating layers, and connected to the substrate, are arranged. A peripheral circuit region includes a row decoder connected to the gate electrodes and a page buffer connected to the channel structures. The memory blocks include main blocks and at least one spare block, wherein a length of the spare block is shorter than a length of each of the main blocks, in a second direction, parallel to the upper surface of the substrate.
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