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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180285104A1

    公开(公告)日：2018-10-04

    申请号：US15717989

    申请日：2017-09-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Pil KIM ,  Hyun Woo SIM ,  Seong Woo AHN

    IPC: G06F9/30 ,  G06F1/32

    CPC classification number: G06F9/3001 ,  G06F1/3287 ,  G06F9/30101

    Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210216312A1

    公开(公告)日：2021-07-15

    申请号：US17216323

    申请日：2021-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Pil KIM ,  Hyun Woo SIM ,  Seong Woo AHN

    IPC: G06F9/30 ,  G06F1/3287 ,  G06T1/20

    Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190018672A9

    公开(公告)日：2019-01-17

    申请号：US15717989

    申请日：2017-09-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Pil KIM ,  Hyun Woo SIM ,  Seong Woo AHN

    IPC: G06F9/30 ,  G06F1/32

    Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

    SEQUENCE ALIGNMENT METHOD OF VECTOR PROCESSOR
    7.
    发明申请
    SEQUENCE ALIGNMENT METHOD OF VECTOR PROCESSOR 审中-公开

    公开(公告)号：US20190303149A1

    公开(公告)日：2019-10-03

    申请号：US16447041

    申请日：2019-06-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun Pil KIM ,  Hyun Woo SIM ,  Seong Woo AHN

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.

    SEQUENCE ALIGNMENT METHOD OF VECTOR PROCESSOR
    8.
    发明申请
    SEQUENCE ALIGNMENT METHOD OF VECTOR PROCESSOR 审中-公开

    公开(公告)号：US20180341487A1

    公开(公告)日：2018-11-29

    申请号：US15802844

    申请日：2017-11-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun Pil KIM ,  Hyun Woo SIM ,  Seong Woo AHN

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/3816 ,  G06F9/3887

    Abstract: A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180300128A1

    公开(公告)日：2018-10-18

    申请号：US15905979

    申请日：2018-02-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Pil KIM ,  Hyun Woo SIM ,  Seong Woo AHN

    IPC: G06F9/30 ,  G06F1/32

    CPC classification number: G06F9/3001 ,  G06F1/3287 ,  G06F9/30101 ,  G06T1/20

    Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

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