公开(公告)号：US20160285452A1

公开(公告)日：2016-09-29

申请号：US15178154

申请日：2016-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAL-HEE LEE ,  JAE-WOO SEO ,  MIN-HO PARK

IPC: H03K19/00 ,  G06F17/50 ,  H03K19/0185

CPC classification number: H03K19/0013 ,  G06F17/5072 ,  H03K19/018507 ,  H03K19/018521 ,  H03K19/0944

Abstract: An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.

公开(公告)号：US20230396241A1

公开(公告)日：2023-12-07

申请号：US18085185

申请日：2022-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Garoom Kim ,  JAE-WOO SEO

IPC: H03K3/037 ,  H03K3/3562 ,  H03K3/012

CPC classification number: H03K3/0372 ,  H03K3/35625 ,  H03K3/012

Abstract: Disclosed is a semiconductor device which includes at least one flip-flop. The flip-flop includes a first latch that includes a first data path receiving input data in response to a transmission signal and outputting middle data, and a first feedback path feeding back the middle data, and a second latch that includes a second data path receiving the middle data in response to the transmission signal and outputting output data, and a second feedback path feeding back the output data, and at least one of the first feedback path and the second feedback path is disabled prior to the first data path or the second data path.

公开(公告)号：US20220020691A1

公开(公告)日：2022-01-20

申请号：US17180491

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONGYU YOU ,  JISU YU ,  JAE-WOO SEO ,  SEUNG MAN LIM

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

公开(公告)号：US20170093401A1

公开(公告)日：2017-03-30

申请号：US15211468

申请日：2016-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAL-HEE LEE ,  JAE-WOO SEO

IPC: H03K19/0185 ,  H03K19/00 ,  H01L27/092

CPC classification number: H03K19/018521 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H03K19/0013

Abstract: An integrated circuit (IC) includes a first circuit, a first well and a second circuit. The first circuit is disposed on a substrate and configured to shift a first bit signal between a first voltage logic level and a second logic voltage level. The first well is disposed in a cell on the substrate and biased to a first voltage. The first well is spaced apart from a first edge of the cell. The second well is disposed in the cell and biased to a second voltage. The second well is disposed to contact a second edge of the cell opposite to the first edge. The first circuit includes a plurality of transistors respectively disposed in the first and second wells.

公开(公告)号：US20210143181A1

公开(公告)日：2021-05-13

申请号：US17153939

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE-WOO SEO ,  KI-MAN PARK ,  HA-YOUNG KIM ,  JUNGHWAN SHIN ,  KEUNHO LEE ,  SUNGWE CHO

IPC: H01L27/118 ,  H01L27/02 ,  H03K3/3562

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

公开(公告)号：US20180189438A1

公开(公告)日：2018-07-05

申请号：US15908291

申请日：2018-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-WOO SEO ,  HA-YOUNG KIM ,  HYUN-JEONG ROH

IPC: G06F17/50

Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

公开(公告)号：US20160125117A1

公开(公告)日：2016-05-05

申请号：US14926128

申请日：2015-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-TAE KIM ,  HA-YOUNG KIM ,  JAE-WOO SEO

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: A method of designing a layout of an integrated circuit (IC), which is implemented by a computer system or a processor, includes receiving input layout data, and performing a design rule check with regard to a plurality of patterns. The method includes, merging, from among a first pattern and a second pattern against the design rule, the first pattern with a third pattern connected to a same net as the first pattern, and generating output layout data.

Abstract translation: 设计由计算机系统或处理器实现的集成电路（IC）的布局的方法包括接收输入布局数据，以及针对多个图案执行设计规则检查。 该方法包括：从第一图案和第二图案中按照设计规则合并具有连接到与第一图案相同的网的第三图案的第一图案，以及生成输出布局数据。

公开(公告)号：US20220375962A1

公开(公告)日：2022-11-24

申请号：US17576279

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjae JEONG ,  JUNGHO DO ,  JAE-WOO SEO ,  JISU YU ,  HYEONGYU YOU

IPC: H01L27/118 ,  H01L27/02 ,  H01L21/768 ,  G03F1/36 ,  G06F30/398

Abstract: A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.

公开(公告)号：US20200161334A1

公开(公告)日：2020-05-21

申请号：US16669639

申请日：2019-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE-WOO SEO ,  KI-MAN PARK ,  HA-YOUNG KIM ,  JUNGHWAN SHIN ,  KEUNHO LEE ,  SUNGWE CHO

IPC: H01L27/118 ,  H01L27/02 ,  H03K3/3562

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.