公开(公告)号：US12237048B2

公开(公告)日：2025-02-25

申请号：US17852593

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hijung Kim ,  Kwangchol Choe ,  Kwangsook Noh ,  Jaepil Lee

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  H03K19/017

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

公开(公告)号：US20240030128A1

公开(公告)日：2024-01-25

申请号：US18204556

申请日：2023-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaepil Lee ,  Junbae Kim ,  Jinkwan Park

IPC: H01L23/522 ,  H10B12/00

CPC classification number: H01L23/5227 ,  H10B12/00

Abstract: A semiconductor device may include a substrate, an element layer including circuit elements arranged on the substrate, a wiring layer on the element layer, and a redistribution layer on the wiring layer. The redistribution layer may include a redistribution insulating layer and a redistribution conductive layer on the redistribution insulating layer. The redistribution conductive layer may include a connection pad and first and second inductor structures respectively including first and second inductor redistribution lines having a planar coil shape, and a connection pad. The first and second inductor redistribution lines respectively included in the first and second inductor structures may have different thicknesses.

公开(公告)号：US10854562B2

公开(公告)日：2020-12-01

申请号：US16867634

申请日：2020-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Ho Shin ,  Bonhwi Gu ,  Hyekyeong Kweon ,  Sungjin Kim ,  Joodong Kim ,  Jaepil Lee ,  Dongwon Lim

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L23/535 ,  H01L23/522 ,  H01L21/66

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.

公开(公告)号：US20230186960A1

公开(公告)日：2023-06-15

申请号：US17852593

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hijung Kim ,  Kwangchol Choe ,  Kwangsook Noh ,  Jaepil Lee

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  H03K19/017

CPC classification number: G11C7/222 ,  G11C7/12 ,  G11C7/1039 ,  G11C8/14 ,  H03K19/01742

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

公开(公告)号：US10679957B2

公开(公告)日：2020-06-09

申请号：US16140252

申请日：2018-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Ho Shin ,  Bonhwi Gu ,  Hyekyeong Kweon ,  Sungjin Kim ,  Joodong Kim ,  Jaepil Lee ,  Dongwon Lim

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/66 ,  H01L23/522 ,  H01L23/535 ,  H01L23/532

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.

公开(公告)号：US20240008265A1

公开(公告)日：2024-01-04

申请号：US18216269

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaepil Lee ,  Junbae Kim

IPC: H10B12/00 ,  H01L23/522 ,  H01F17/00

CPC classification number: H10B12/482 ,  H01L28/90 ,  H01L23/5227 ,  H01L28/10 ,  H01F17/0013 ,  H10B12/50 ,  H10B12/34 ,  H10B12/315 ,  H01F2017/0073

Abstract: A semiconductor device includes a lower structure, a data storage structure on the lower structure, and an inductor structure on the lower structure, where the data storage structure includes first electrodes extending in a vertical direction perpendicular to an upper surface of the lower structure, a second electrode provided on the first electrodes, and a dielectric layer between the first electrodes and the second electrode, and where the inductor structure includes an inductor conductive pattern at a level that is substantially the same as a level of the first electrodes.