公开(公告)号：US20200091176A1

公开(公告)日：2020-03-19

申请号：US16288449

申请日：2019-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-gn YUN ,  Jae-duk LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  H01L29/792 ,  H01L29/66

Abstract: An integrated circuit device includes word line structures, insulating structures, a channel hole, and charge trap patterns. The word line structures and the insulating structures are interleaved with each other and extend in a horizontal direction parallel to a main surface of a substrate, and overlap one another in a vertical direction. The channel hole passes through the word line structures and the insulating structures in the vertical direction. The charge trap patterns are located in the channel hole, and are spaced apart from one another in the vertical direction with a local insulating region therebetween.

公开(公告)号：US20200273501A1

公开(公告)日：2020-08-27

申请号：US16675273

申请日：2019-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-gn YUN ,  Jae-Duk LEE ,  Jai-Hyuk SONG

IPC: G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

公开(公告)号：US20240347455A1

公开(公告)日：2024-10-17

申请号：US18508757

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-gn YUN ,  Jeehoon HAN ,  Hyunho KIM

IPC: H01L23/528 ,  G11C5/06 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C5/063 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/0651

Abstract: A semiconductor device including a first conductive pattern having a first connection part and a plurality of first branch parts connected to the first connection part, a second conductive pattern having a second connection part and a plurality of second branch parts connected to the second connection part, a first memory channel structure in contact with a corresponding one of the first branch parts and a corresponding one of the second branch parts, and a gate cutting pattern in contact with the corresponding one of the second branch parts and the first connection part may be provided. The first conductive pattern and the second conductive pattern may be spaced apart from each other.

公开(公告)号：US20200091084A1

公开(公告)日：2020-03-19

申请号：US16689628

申请日：2019-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-woo KIM ,  Joon-sung LIM ,  Jang-gn YUN ,  Sung-min HWANG

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.

公开(公告)号：US20180254247A1

公开(公告)日：2018-09-06

申请号：US15822329

申请日：2017-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-woo KIM ,  Joon-sung LIM ,  Jang-gn YUN ,  Sung-min Hwang

IPC: H01L23/532 ,  H01L27/11531 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L23/53295 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/1207

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.