公开(公告)号：US11574912B2

公开(公告)日：2023-02-07

申请号：US17112195

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo Hong ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US09337151B2

公开(公告)日：2016-05-10

申请号：US14457185

申请日：2014-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min Park ,  Yoo-Sang Hwang

IPC: H01L29/68 ,  H01L21/768 ,  H01L29/94 ,  H01L21/4763 ,  H01L23/538 ,  H01L23/535 ,  H01L27/108

CPC classification number: H01L23/5386 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate having a contact region. An interlayer insulating layer is disposed on the semiconductor substrate. A lower contact plug passing through the interlayer insulating layer and electrically connected to the contact region is disposed. An interconnection structure is disposed on the interlayer insulating layer. An adjacent interconnection spaced apart from the interconnection structure is disposed on the interlayer insulating layer. A bottom surface of the interconnection structure includes a first part overlapping a part of an upper surface of the lower contact plug, and a second part overlapping the interlayer insulating layer.

Abstract translation: 提供一种半导体器件。 半导体器件包括具有接触区域的半导体衬底。 层间绝缘层设置在半导体衬底上。 设置穿过层间绝缘层并电连接到接触区域的下接触插塞。 互连结构设置在层间绝缘层上。 与互连结构间隔开的相邻互连设置在层间绝缘层上。 互连结构的底表面包括与下接触插塞的上表面的一部分重叠的第一部分和与层间绝缘层重叠的第二部分。

公开(公告)号：US10886277B2

公开(公告)日：2021-01-05

申请号：US16106087

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo Hong ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US09196620B2

公开(公告)日：2015-11-24

申请号：US14017502

申请日：2013-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Park ,  Dae-Ik Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L29/423 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/10894 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/5222 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer.

Abstract translation: 半导体器件包括在第一区域中的衬底上的绝缘中间层，所述绝缘层包括暴露衬底表面的一部分的接触孔以及接触孔中的接触插塞。 接触插塞包括第一阻挡金属层图案和第一金属层图案的堆叠结构。 半导体器件还包括与接触插塞直接接触的第二金属层图案和绝缘中间层的上表面。 第二金属层图案是金属材料层。

公开(公告)号：US10332831B2

公开(公告)日：2019-06-25

申请号：US15638552

申请日：2017-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Augustin Jinwoo Hong ,  Dae-Ik Kim ,  Chan-Sic Yoon ,  Ki-Seok Lee ,  Dong-Min Han ,  Sung-Ho Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

IPC: H01L27/108 ,  H01L23/522 ,  H01L27/11568 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

公开(公告)号：US09960039B2

公开(公告)日：2018-05-01

申请号：US15291780

申请日：2016-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik Kim ,  Eun-Jung Kim ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/308 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816

Abstract: A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.

公开(公告)号：US09379118B2

公开(公告)日：2016-06-28

申请号：US14303142

申请日：2014-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Park

IPC: H01L21/00 ,  H01L27/108

CPC classification number: H01L27/10897 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5283 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of fabricating the same are disclosed. The methods include forming a first interlayer insulating layer and a conductive contact plug that penetrates the first interlayer insulating layer, forming a second interlayer insulating layer and a first interlayer wiring on the first interlayer insulating layer. The first interlayer wiring penetrates the second interlayer insulating layer and overlaps the first metal contact plug. The second interlayer insulating layer is etched using the first interlayer wiring as a mask until the first metal contact plug is exposed, and an exposed portion of the conductive contact plug is etched using the first interlayer wiring as the mask.

Abstract translation: 公开了半导体器件及其制造方法。 所述方法包括在第一层间绝缘层上形成穿透第一层间绝缘层的第一层间绝缘层和导电接触塞，形成第二层间绝缘层和第一层间布线。 第一层间布线穿透第二层间绝缘层并与第一金属接触插塞重叠。 使用第一层间布线作为掩模蚀刻第二层间绝缘层，直到第一金属接触插塞露出，并且使用第一层间布线作为掩模来蚀刻导电接触插塞的暴露部分。

公开(公告)号：US20190139963A1

公开(公告)日：2019-05-09

申请号：US16106087

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo HONG ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L23/535 ,  H01L21/768

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US09559103B2

公开(公告)日：2017-01-31

申请号：US14716594

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min Park ,  Tae-Jin Park ,  Yong-Kwan Kim ,  Yoo-Sang Hwang

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894

Abstract: Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.

Abstract translation: 提供了一种存储器件。 存储装置包括：基板，包括单元区域和周边区域; 栅极线堆叠和位线堆叠被配置为在单元区域中垂直交叉; 埋设的触点设置在由相邻栅极线堆叠和相邻位线堆叠同时共享的区域中; 扩展的着陆焊盘，包括连接到埋入触点的扩展部分，并在相邻位线堆叠上扩展，并且布置成一排; 与扩展的着陆焊盘间隔开的着陆焊盘作为柱，连接到埋置的触点，并且具有比扩展的焊盘的水平宽度小的水平宽度; 以及连接到扩展的着陆焊盘的扩展部分的第一存储节点，以及连接到着陆焊盘的第二存储节点。

公开(公告)号：US09318369B2

公开(公告)日：2016-04-19

申请号：US14175257

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Park

IPC: H01L29/00 ,  H01L21/762 ,  H01L21/76 ,  H01L27/108

CPC classification number: H01L21/76229 ,  H01L21/76 ,  H01L27/10876 ,  H01L27/10894

Abstract: A semiconductor device including a plurality of active patterns, a plurality of first isolation layer patterns and a plurality of second isolation layer patterns may be provided. In particular, the active patterns may be arranged both in a first direction and in a second direction, and may protrude from a substrate and have a length in the first direction. The first isolation layer patterns may fill a first space, the first space provided between the active patterns and arranged in the first direction, and support two opposing sidewalls of neighboring active patterns. The second isolation layer patterns may fill a second space between the active patterns and the first isolation layer patterns. Accordingly, the active patterns of the semiconductor device may not collapse or incline because the first isolation layer patterns support the active patterns.

Abstract translation: 可以提供包括多个有源图案，多个第一隔离层图案和多个第二隔离层图案的半导体器件。 特别地，有源图案可以在第一方向和第二方向上布置，并且可以从基板突出并且在第一方向上具有长度。 第一隔离层图案可以填充第一空间，第一空间设置在活动图案之间并且布置在第一方向上，并且支撑相邻活动图案的两个相对的侧壁。 第二隔离层图案可以填充活性图案和第一隔离层图案之间的第二空间。 因此，半导体器件的有源图案可能不会折叠或倾斜，因为第一隔离层图案支持活动图案。