中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.014 seconds)

    System on chip including a multi-core processor and task scheduling method thereof
    3.
    发明授权
    System on chip including a multi-core processor and task scheduling method thereof 有权

    公开(公告)号：US11243806B2

    公开(公告)日：2022-02-08

    申请号：US16518159

    申请日：2019-07-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Lae Park ,  Soohyun Kim ,  Youngtae Lee ,  Byung-Soo Kwon

    IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

    Abstract: A scheduling method of a system on chip including a multi-core processor includes receiving a schedule-requested task, converting a priority assigned to the schedule-requested task into a linear priority weight, selecting a plurality of candidate cores, to which the schedule-requested task will be assigned, from among cores of the multi-core processor, calculating a preemption compare index indicating a current load state of each of the plurality of candidate cores, comparing the linear priority weight with the preemption compare index of the each of the plurality of candidate cores to generate a comparison result, and assigning the schedule-requested task to one candidate core of the plurality of candidate cores depending on the comparison result.

    System-on-chip having a symmetric multi-processor and method of determining a maximum operating clock frequency for the same
    4.
    发明授权
    System-on-chip having a symmetric multi-processor and method of determining a maximum operating clock frequency for the same 有权

    公开(公告)号：US10042731B2

    公开(公告)日：2018-08-07

    申请号：US14453106

    申请日：2014-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Lae Park ,  Byeong-Jun Lee

    IPC: G06F1/32 ,  G06F11/30 ,  G06F1/20

    Abstract: A system-on-chip includes a symmetric multi-processor including a plurality of cores, each configured to operate in a high performance operating mode and a low performance operating mode. The system-on-chip further includes a clock management unit configured to provide an operating clock signal to the symmetric multi-processor, a state management unit configured to monitor operating states of the cores, a temperature management unit configured to monitor a temperature of the symmetric multi-processor, and a symmetric multi-processor control unit configured to determine the operating clock signal and the operating states of the cores based on a workload of the symmetric multi-processor. The symmetric multi-processor control unit is further configured to differentially determine a maximum operating clock frequency for the cores based on the temperature and the operating states of the cores, which indicate a quantity of cores that are currently in operation.

    SYSTEM-ON-CHIP AND AN OPERATING METHOD THEREOF
    5.
    发明申请
    SYSTEM-ON-CHIP AND AN OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230071632A1

    公开(公告)日：2023-03-09

    申请号：US17720483

    申请日：2022-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHOONGHOON PARK ,  Jong-Lae Park ,  Bumgyu Park ,  Youngtae Lee ,  Donghee Han

    IPC: G05F1/66 ,  G05F1/46 ,  G06F1/3296 ,  G06F1/3234 ,  G06F15/78

    Abstract: An operating method of a system-on-chip (SoC) which includes a processor including a first core and a dynamic voltage and frequency scaling (DVFS) module and a clock management unit (CMU) for supplying an operating clock to the first core, the operating method including: obtaining a required performance of the first core; finding available frequencies meeting the required performance; obtaining information for calculating energy consumption for each of the available frequencies; calculating the energy consumption for each of the available frequencies, based on the information; determining a frequency, which causes minimum energy consumption, from among the available frequencies as an optimal frequency; and
    adjusting an operating frequency to be supplied to the first core to the optimal frequency.

    Method of dynamically scaling a power level of a microprocessor
    7.
    发明授权
    Method of dynamically scaling a power level of a microprocessor 有权
    动态缩放微处理器功率电平的方法

    公开(公告)号：US09239614B2

    公开(公告)日：2016-01-19

    申请号：US14152401

    申请日：2014-01-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Lae Park

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A method of dynamically scaling a power level of a microprocessor is provided. The method includes: receiving a plurality of workload rates of a microprocessor in a first duration period; determining a second duration period by adjusting a length of the first duration period; calculating a period workload rate based on the plurality of workload rates in the first duration period; dynamically scaling a power level of the microprocessor; and maintaining the scaled power level of the microprocessor in the second duration period.

    Abstract translation: 提供了一种动态缩放微处理器功率电平的方法。 该方法包括：在第一持续时间段内接收微处理器的多个工作负载率; 通过调整所述第一持续时间段的长度来确定第二持续时间段; 基于所述第一持续时间段中的所述多个工作负载率来计算周期工作负载率; 动态地缩放微处理器的功率电平; 以及在第二持续时间段内保持微处理器的缩放功率电平。

Patent Agency Ranking