公开(公告)号：US20220278061A1

公开(公告)日：2022-09-01

申请号：US17747190

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyoung Jeong ,  Juik Lee ,  Junghoon Han

IPC: H01L23/00

Abstract: Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

公开(公告)号：US11616018B2

公开(公告)日：2023-03-28

申请号：US17398043

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik Lee ,  Joongwon Shin ,  Jihoon Chang ,  Junghoon Han ,  Junwoo Lee

IPC: H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

公开(公告)号：US11133253B2

公开(公告)日：2021-09-28

申请号：US16885438

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik Lee ,  Joongwon Shin ,  Jihoon Chang ,  Junghoon Han ,  Junwoo Lee

IPC: H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

公开(公告)号：US11769742B2

公开(公告)日：2023-09-26

申请号：US17747190

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyoung Jeong ,  Juik Lee ,  Junghoon Han

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L2224/05583

Abstract: Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

公开(公告)号：US20210134745A1

公开(公告)日：2021-05-06

申请号：US16922828

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyoung Jeong ,  Juik Lee ,  Junghoon Han

IPC: H01L23/00

Abstract: Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

公开(公告)号：US10332842B2

公开(公告)日：2019-06-25

申请号：US16026937

申请日：2018-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Sooho Shin ,  Juik Lee ,  Jun Ho Lee ,  Kwangmin Kim ,  Ilyoung Moon ,  Jemin Park ,  Bumseok Seo ,  Chan-Sic Yoon ,  Hoin Lee

IPC: H01L23/544 ,  H01L27/108

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

公开(公告)号：US12288734B2

公开(公告)日：2025-04-29

申请号：US17714202

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juik Lee ,  Jong-Min Lee ,  Jimin Choi ,  Yeonjin Lee ,  Jeon Il Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.

公开(公告)号：US20250062255A1

公开(公告)日：2025-02-20

申请号：US18670055

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong PARK ,  Jongmin Lee ,  Nara Lee ,  Juik Lee

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor chip includes a semiconductor substrate including an active surface and an inactive surface opposite to the active surface, a wiring layer on the active surface, a front connection pad on the wiring layer, a lower protective insulating layer at least partially covering the wiring layer and including a lower opening that exposes at least a portion of the front connection pad, an upper protective insulating layer including an upper opening communicatively coupled to the lower opening on the lower protective insulating layer, a connection terminal coupled to the front connection pad through the lower opening and the upper opening, and an upper cover insulating layer between the connection terminal and the upper protective insulating layer. The upper protective insulating layer includes an organic material. The upper cover insulating layer includes an inorganic material.

公开(公告)号：US12040231B2

公开(公告)日：2024-07-16

申请号：US17201457

申请日：2021-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon Han ,  Juik Lee

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/528

Abstract: A semiconductor device includes a substrate, an interlayer insulating layer covering an upper surface of the substrate, an individual device in the interlayer insulating layer, a lower insulating layer covering a lower surface of the substrate, a through-silicon-via (TSV) structure extending through the substrate, the interlayer insulating layer and the lower insulating layer, a conductive pad connected to an upper end of the TSV structure, a via insulating layer surrounding the TSV structure, a capping insulating layer surrounding the TSV structure outside the via insulating layer. The via insulating layer and the capping insulating layer have an air gap therebetween. A portion of the air gap extends into the lower insulating layer.

公开(公告)号：US20180096947A1

公开(公告)日：2018-04-05

申请号：US15608747

申请日：2017-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KISEOK LEE ,  Sooho Shin ,  Juik Lee ,  Jun Ho Lee ,  Kwangmin Kim ,  Ilyoung Moon ,  Jemin Park ,  Bumseok Seo ,  Chan-Sic Yoon ,  Hoin Lee

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.